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https://github.com/brain-hackers/u-boot-brain
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a129f64fb0
Currently on Armada-37xx the mem_map structure is statically defined to map first 2 GB of memory as RAM region, and system registers and PCIe region device region. This is insufficient for when there is more RAM or when for example the PCIe windows is mapped to another address by the CPU Address Decoder. In the case when the board has 4 GB RAM, on some boards the ARM Trusted Firmware can move the PCIe window to another address, in order to maximize possible usable RAM. Also the dram_init and dram_init_banksize looks for information in device-tree, and therefore different device trees are needed for boards with different RAM sizes. Therefore we add code that looks at how the ARM Trusted Firmware has configured the CPU Address Decoder windows, and then we update the mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank base addresses and sizes accordingly. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
111 lines
2.3 KiB
C
111 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <linux/libfdt.h>
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#include <linux/sizes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Not all memory is mapped in the MMU. So we need to restrict the
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* memory size so that U-Boot does not try to access it. Also, the
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* internal registers are located at 0xf000.0000 - 0xffff.ffff.
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* Currently only 2GiB are mapped for system memory. This is what
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* we pass to the U-Boot subsystem here.
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*/
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#define USABLE_RAM_SIZE 0x80000000
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ulong board_get_usable_ram_top(ulong total_size)
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{
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if (gd->ram_size > USABLE_RAM_SIZE)
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return USABLE_RAM_SIZE;
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return gd->ram_size;
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}
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/*
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* On ARMv8, MBus is not configured in U-Boot. To enable compilation
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* of the already implemented drivers, lets add a dummy version of
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* this function so that linking does not fail.
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*/
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const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
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{
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return NULL;
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}
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__weak int dram_init_banksize(void)
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{
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if (CONFIG_IS_ENABLED(ARMADA_8K))
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return a8k_dram_init_banksize();
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else if (CONFIG_IS_ENABLED(ARMADA_3700))
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return a3700_dram_init_banksize();
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else
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return fdtdec_setup_memory_banksize();
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}
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__weak int dram_init(void)
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{
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if (CONFIG_IS_ENABLED(ARMADA_8K)) {
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gd->ram_size = a8k_dram_scan_ap_sz();
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if (gd->ram_size != 0)
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return 0;
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}
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if (CONFIG_IS_ENABLED(ARMADA_3700))
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return a3700_dram_init();
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int arch_cpu_init(void)
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{
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/* Nothing to do (yet) */
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return 0;
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}
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int arch_early_init_r(void)
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{
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struct udevice *dev;
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int ret;
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int i;
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/*
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* Loop over all MISC uclass drivers to call the comphy code
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* and init all CP110 devices enabled in the DT
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*/
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i = 0;
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while (1) {
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/* Call the comphy code via the MISC uclass driver */
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ret = uclass_get_device(UCLASS_MISC, i++, &dev);
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/* We're done, once no further CP110 device is found */
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if (ret)
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break;
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}
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/* Cause the SATA device to do its early init */
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uclass_first_device(UCLASS_AHCI, &dev);
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#ifdef CONFIG_DM_PCI
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/* Trigger PCIe devices detection */
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pci_init();
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#endif
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return 0;
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}
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