mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
299 lines
7.0 KiB
C
299 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <log.h>
|
|
#include <dm/pinctrl.h>
|
|
#include <regmap.h>
|
|
#include <syscon.h>
|
|
#include <linux/bitops.h>
|
|
|
|
#include "pinctrl-rockchip.h"
|
|
|
|
static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
|
|
{
|
|
.num = 1,
|
|
.pin = 0,
|
|
.reg = 0x418,
|
|
.bit = 0,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 1,
|
|
.reg = 0x418,
|
|
.bit = 2,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 2,
|
|
.reg = 0x418,
|
|
.bit = 4,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 3,
|
|
.reg = 0x418,
|
|
.bit = 6,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 4,
|
|
.reg = 0x418,
|
|
.bit = 8,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 5,
|
|
.reg = 0x418,
|
|
.bit = 10,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 6,
|
|
.reg = 0x418,
|
|
.bit = 12,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 7,
|
|
.reg = 0x418,
|
|
.bit = 14,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 8,
|
|
.reg = 0x41c,
|
|
.bit = 0,
|
|
.mask = 0x3
|
|
}, {
|
|
.num = 1,
|
|
.pin = 9,
|
|
.reg = 0x41c,
|
|
.bit = 2,
|
|
.mask = 0x3
|
|
},
|
|
};
|
|
|
|
static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
|
{
|
|
struct rockchip_pinctrl_priv *priv = bank->priv;
|
|
int iomux_num = (pin / 8);
|
|
struct regmap *regmap;
|
|
int reg, ret, mask, mux_type;
|
|
u8 bit;
|
|
u32 data;
|
|
|
|
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
|
|
? priv->regmap_pmu : priv->regmap_base;
|
|
|
|
/* get basic quadrupel of mux registers and the correct reg inside */
|
|
mux_type = bank->iomux[iomux_num].type;
|
|
reg = bank->iomux[iomux_num].offset;
|
|
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
|
|
|
|
if (bank->recalced_mask & BIT(pin))
|
|
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
|
|
|
|
data = (mask << (bit + 16));
|
|
data |= (mux & mask) << bit;
|
|
ret = regmap_write(regmap, reg, data);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define RV1108_PULL_PMU_OFFSET 0x10
|
|
#define RV1108_PULL_OFFSET 0x110
|
|
|
|
static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
|
|
int pin_num, struct regmap **regmap,
|
|
int *reg, u8 *bit)
|
|
{
|
|
struct rockchip_pinctrl_priv *priv = bank->priv;
|
|
|
|
/* The first 24 pins of the first bank are located in PMU */
|
|
if (bank->bank_num == 0) {
|
|
*regmap = priv->regmap_pmu;
|
|
*reg = RV1108_PULL_PMU_OFFSET;
|
|
} else {
|
|
*reg = RV1108_PULL_OFFSET;
|
|
*regmap = priv->regmap_base;
|
|
/* correct the offset, as we're starting with the 2nd bank */
|
|
*reg -= 0x10;
|
|
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
|
|
}
|
|
|
|
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
|
|
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
|
|
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
|
|
}
|
|
|
|
static int rv1108_set_pull(struct rockchip_pin_bank *bank,
|
|
int pin_num, int pull)
|
|
{
|
|
struct regmap *regmap;
|
|
int reg, ret;
|
|
u8 bit, type;
|
|
u32 data;
|
|
|
|
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
|
|
return -ENOTSUPP;
|
|
|
|
rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
|
type = bank->pull_type[pin_num / 8];
|
|
ret = rockchip_translate_pull_value(type, pull);
|
|
if (ret < 0) {
|
|
debug("unsupported pull setting %d\n", pull);
|
|
return ret;
|
|
}
|
|
|
|
/* enable the write to the equivalent lower bits */
|
|
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
|
|
|
data |= (ret << bit);
|
|
ret = regmap_write(regmap, reg, data);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define RV1108_DRV_PMU_OFFSET 0x20
|
|
#define RV1108_DRV_GRF_OFFSET 0x210
|
|
|
|
static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
|
int pin_num, struct regmap **regmap,
|
|
int *reg, u8 *bit)
|
|
{
|
|
struct rockchip_pinctrl_priv *priv = bank->priv;
|
|
|
|
/* The first 24 pins of the first bank are located in PMU */
|
|
if (bank->bank_num == 0) {
|
|
*regmap = priv->regmap_pmu;
|
|
*reg = RV1108_DRV_PMU_OFFSET;
|
|
} else {
|
|
*regmap = priv->regmap_base;
|
|
*reg = RV1108_DRV_GRF_OFFSET;
|
|
|
|
/* correct the offset, as we're starting with the 2nd bank */
|
|
*reg -= 0x10;
|
|
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
|
|
}
|
|
|
|
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
|
|
*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
|
|
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
|
|
}
|
|
|
|
static int rv1108_set_drive(struct rockchip_pin_bank *bank,
|
|
int pin_num, int strength)
|
|
{
|
|
struct regmap *regmap;
|
|
int reg, ret;
|
|
u32 data;
|
|
u8 bit;
|
|
int type = bank->drv[pin_num / 8].drv_type;
|
|
|
|
rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
|
ret = rockchip_translate_drive_value(type, strength);
|
|
if (ret < 0) {
|
|
debug("unsupported driver strength %d\n", strength);
|
|
return ret;
|
|
}
|
|
|
|
/* enable the write to the equivalent lower bits */
|
|
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
|
|
|
|
data |= (ret << bit);
|
|
ret = regmap_write(regmap, reg, data);
|
|
return ret;
|
|
}
|
|
|
|
#define RV1108_SCHMITT_PMU_OFFSET 0x30
|
|
#define RV1108_SCHMITT_GRF_OFFSET 0x388
|
|
#define RV1108_SCHMITT_BANK_STRIDE 8
|
|
#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
|
|
#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
|
|
|
|
static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
|
int pin_num,
|
|
struct regmap **regmap,
|
|
int *reg, u8 *bit)
|
|
{
|
|
struct rockchip_pinctrl_priv *priv = bank->priv;
|
|
int pins_per_reg;
|
|
|
|
if (bank->bank_num == 0) {
|
|
*regmap = priv->regmap_pmu;
|
|
*reg = RV1108_SCHMITT_PMU_OFFSET;
|
|
pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
|
|
} else {
|
|
*regmap = priv->regmap_base;
|
|
*reg = RV1108_SCHMITT_GRF_OFFSET;
|
|
pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
|
|
*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
|
|
}
|
|
*reg += ((pin_num / pins_per_reg) * 4);
|
|
*bit = pin_num % pins_per_reg;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
|
|
int pin_num, int enable)
|
|
{
|
|
struct regmap *regmap;
|
|
int reg;
|
|
u8 bit;
|
|
u32 data;
|
|
|
|
rv1108_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
|
/* enable the write to the equivalent lower bits */
|
|
data = BIT(bit + 16) | (enable << bit);
|
|
|
|
return regmap_write(regmap, reg, data);
|
|
}
|
|
|
|
static struct rockchip_pin_bank rv1108_pin_banks[] = {
|
|
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
|
|
IOMUX_SOURCE_PMU,
|
|
IOMUX_SOURCE_PMU,
|
|
IOMUX_SOURCE_PMU),
|
|
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
|
|
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
|
|
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
|
|
};
|
|
|
|
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
|
|
.pin_banks = rv1108_pin_banks,
|
|
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
|
|
.grf_mux_offset = 0x10,
|
|
.pmu_mux_offset = 0x0,
|
|
.iomux_recalced = rv1108_mux_recalced_data,
|
|
.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
|
|
.set_mux = rv1108_set_mux,
|
|
.set_pull = rv1108_set_pull,
|
|
.set_drive = rv1108_set_drive,
|
|
.set_schmitt = rv1108_set_schmitt,
|
|
};
|
|
|
|
static const struct udevice_id rv1108_pinctrl_ids[] = {
|
|
{
|
|
.compatible = "rockchip,rv1108-pinctrl",
|
|
.data = (ulong)&rv1108_pin_ctrl
|
|
},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pinctrl_rv1108) = {
|
|
.name = "pinctrl_rv1108",
|
|
.id = UCLASS_PINCTRL,
|
|
.of_match = rv1108_pinctrl_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
|
|
.ops = &rockchip_pinctrl_ops,
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
.bind = dm_scan_fdt_dev,
|
|
#endif
|
|
.probe = rockchip_pinctrl_probe,
|
|
};
|