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8995a96d1d
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY. The PHY acts as a generic PHY but needs a slight configuration right before it's configuration. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/*
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* Meson GXL Internal PHY Driver
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2016 BayLibre, SAS. All rights reserved.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <linux/bitops.h>
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#include <phy.h>
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static int meson_gxl_phy_config(struct phy_device *phydev)
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{
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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/* Write Analog register 23 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
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/* Enable fractional PLL */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
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return genphy_config(phydev);
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}
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static struct phy_driver meson_gxl_phy_driver = {
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.name = "Meson GXL Internal PHY",
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.uid = 0x01814400,
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.mask = 0xfffffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &meson_gxl_phy_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_meson_gxl_init(void)
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{
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phy_register(&meson_gxl_phy_driver);
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return 0;
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}
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