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https://github.com/brain-hackers/u-boot-brain
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b259732d36
Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [York Sun: Reformatted commit message slightly] Reviewed-by: York Sun <york.sun@nxp.com>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* Common internal memory map for some Freescale SoCs
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*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SEC_MON_H
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#define __FSL_SEC_MON_H
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#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYS_FSL_SEC_MON_LE
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#define sec_mon_in32(a) in_le32(a)
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#define sec_mon_out32(a, v) out_le32(a, v)
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#define sec_mon_in16(a) in_le16(a)
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#define sec_mon_clrbits32 clrbits_le32
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#define sec_mon_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
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#define sec_mon_in32(a) in_be32(a)
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#define sec_mon_out32(a, v) out_be32(a, v)
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#define sec_mon_in16(a) in_be16(a)
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#define sec_mon_clrbits32 clrbits_be32
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#define sec_mon_setbits32 setbits_be32
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#else
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#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
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#endif
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struct ccsr_sec_mon_regs {
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u8 reserved0[0x04];
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u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
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u8 reserved2[0x0c];
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u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
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};
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#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
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#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
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#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
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#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
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#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
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#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
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#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
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#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
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#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
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#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */
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#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
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/*
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* SEC_MON read. This specifies the possible reads
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* from the SEC_MON
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*/
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enum {
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SEC_MON_SSM_ST,
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SEC_MON_SW_FSV,
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SEC_MON_SW_SV,
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};
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/* Transition SEC_MON state */
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int set_sec_mon_state(u32 state);
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#endif /* __FSL_SEC_MON_H */
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