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https://github.com/brain-hackers/u-boot-brain
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706865afe5
This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/post.h>
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#include <asm/arch/device.h>
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#include <asm/arch/tnc.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/processor.h>
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static int __maybe_unused disable_igd(void)
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{
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struct udevice *igd, *sdvo;
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int ret;
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ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
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if (ret)
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return ret;
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if (!igd)
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return 0;
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ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
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if (ret)
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return ret;
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if (!sdvo)
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return 0;
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/*
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* According to Atom E6xx datasheet, setting VGA Disable (bit17)
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* of Graphics Controller register (offset 0x50) prevents IGD
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* (D2:F0) from reporting itself as a VGA display controller
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* class in the PCI configuration space, and should also prevent
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* it from responding to VGA legacy memory range and I/O addresses.
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*
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* However test result shows that with just VGA Disable bit set and
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* a PCIe graphics card connected to one of the PCIe controllers on
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* the E6xx, accessing the VGA legacy space still causes system hang.
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* After a number of attempts, it turns out besides VGA Disable bit,
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* the SDVO (D3:F0) device should be disabled to make it work.
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*
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* To simplify, use the Function Disable register (offset 0xc4)
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* to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
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* two devices will be completely disabled (invisible in the PCI
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* configuration space) unless a system reset is performed.
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*/
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dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
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dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
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/*
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* After setting the function disable bit, IGD and SDVO devices will
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* disappear in the PCI configuration space. This however creates an
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* inconsistent state from a driver model PCI controller point of view,
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* as these two PCI devices are still attached to its parent's child
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* device list as maintained by the driver model. Some driver model PCI
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* APIs like dm_pci_find_class(), are referring to the list to speed up
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* the finding process instead of re-enumerating the whole PCI bus, so
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* it gets the stale cached data which is wrong.
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*
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* Note x86 PCI enueration normally happens twice, in pre-relocation
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* phase and post-relocation. One option might be to call disable_igd()
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* in one of the pre-relocation initialization hooks so that it gets
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* disabled in the first round, and when it comes to the second round
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* driver model PCI will construct a correct list. Unfortunately this
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* does not work as Intel FSP is used on this platform to perform low
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* level initialization, and fsp_init_phase_pci() is called only once
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* in the post-relocation phase. If we disable IGD and SDVO devices,
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* fsp_init_phase_pci() simply hangs and never returns.
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*
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* So the only option we have is to manually remove these two devices.
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*/
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ret = device_remove(igd, DM_REMOVE_NORMAL);
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if (ret)
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return ret;
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ret = device_unbind(igd);
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if (ret)
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return ret;
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ret = device_remove(sdvo, DM_REMOVE_NORMAL);
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if (ret)
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return ret;
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ret = device_unbind(sdvo);
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if (ret)
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return ret;
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return 0;
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int arch_early_init_r(void)
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{
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int ret = 0;
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#ifdef CONFIG_DISABLE_IGD
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ret = disable_igd();
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#endif
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return ret;
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}
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