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https://github.com/brain-hackers/u-boot-brain
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98f705c9ce
There was for long time no activity in the 4xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 4xx, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
109 lines
2.7 KiB
ArmAsm
109 lines
2.7 KiB
ArmAsm
/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
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* Copyright Freescale Semiconductor, Inc. 2004, 2006.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbf */
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/* Description: Data Cache block flush */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbf
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ppcDcbf:
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dcbf r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbi */
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/* Description: Data Cache block Invalidate */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbi
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ppcDcbi:
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dcbi r0,r3
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blr
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/*--------------------------------------------------------------------------
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* Function: ppcDcbz
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* Description: Data Cache block zero.
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* Input: r3 = effective address
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* Output: none.
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*-------------------------------------------------------------------------- */
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.globl ppcDcbz
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ppcDcbz:
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dcbz r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcSync */
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/* Description: Processor Synchronize */
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/* Input: none. */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcSync
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ppcSync:
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sync
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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#endif
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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sync
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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#endif
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blr
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