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5991d0e36d
Since all DTS files has been switched to "jedec,spi-nor", remove the "spi-flash" compatible from the bindings examples. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
40 lines
1.2 KiB
Plaintext
40 lines
1.2 KiB
Plaintext
STM32 QSPI controller device tree bindings
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--------------------------------------------
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Required properties:
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- compatible : should be "st,stm32-qspi".
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- reg : 1. Physical base address and size of SPI registers map.
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2. Physical base address & size of mapped NOR Flash.
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- spi-max-frequency : Max supported spi frequency.
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- status : enable in requried dts.
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Connected flash properties
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--------------------------
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- spi-max-frequency : Max supported spi frequency.
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- spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
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- spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
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- memory-map : Address and size for memory-mapping the flash
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Example:
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qspi: quadspi@A0001000 {
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compatible = "st,stm32-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <92>;
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spi-max-frequency = <108000000>;
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status = "okay";
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qflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a13", "jedec,spi-nor";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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memory-map = <0x90000000 0x1000000>;
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reg = <0>;
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};
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};
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