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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
116 lines
2.8 KiB
Plaintext
116 lines
2.8 KiB
Plaintext
if ARCH_UNIPHIER
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config SYS_CONFIG_NAME
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default "uniphier"
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config ARCH_UNIPHIER_32BIT
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bool
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select ARMV7_NONSEC
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config ARCH_UNIPHIER_64BIT
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bool
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select ARM64
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select SPL_SEPARATE_BSS
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select ARMV8_MULTIENTRY
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select ARMV8_SPIN_TABLE
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choice
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prompt "UniPhier SoC select"
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default ARCH_UNIPHIER_PRO4
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config ARCH_UNIPHIER_SLD3
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bool "UniPhier PH1-sLD3 SoC"
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select ARCH_UNIPHIER_32BIT
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config ARCH_UNIPHIER_LD4_SLD8
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bool "UniPhier PH1-LD4/PH1-sLD8 SoC"
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select ARCH_UNIPHIER_32BIT
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config ARCH_UNIPHIER_PRO4
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bool "UniPhier PH1-Pro4 SoC"
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select ARCH_UNIPHIER_32BIT
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config ARCH_UNIPHIER_PRO5_PXS2_LD6B
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bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
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select ARCH_UNIPHIER_32BIT
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config ARCH_UNIPHIER_LD11
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bool "UniPhier PH1-LD11 SoC"
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select ARCH_UNIPHIER_64BIT
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config ARCH_UNIPHIER_LD20
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bool "UniPhier PH1-LD20 SoC"
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select ARCH_UNIPHIER_64BIT
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select OF_BOARD_SETUP
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endchoice
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config ARCH_UNIPHIER_LD4
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bool "Enable UniPhier PH1-LD4 SoC support"
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depends on ARCH_UNIPHIER_LD4_SLD8
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default y
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config ARCH_UNIPHIER_SLD8
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bool "Enable UniPhier PH1-sLD8 SoC support"
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depends on ARCH_UNIPHIER_LD4_SLD8
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default y
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config ARCH_UNIPHIER_PRO5
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bool "Enable UniPhier PH1-Pro5 SoC support"
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depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
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default y
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config ARCH_UNIPHIER_PXS2
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bool "Enable UniPhier ProXstream2 SoC support"
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depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
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default y
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config ARCH_UNIPHIER_LD6B
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bool "Enable UniPhier PH1-LD6b SoC support"
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depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
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default y
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config CACHE_UNIPHIER
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bool "Enable the UniPhier L2 cache controller"
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depends on ARCH_UNIPHIER_32BIT
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select SYS_CACHE_SHIFT_7
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default y
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help
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This option allows to use the UniPhier System Cache as L2 cache.
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config MICRO_SUPPORT_CARD
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bool "Use Micro Support Card"
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help
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This option provides support for the expansion board, available
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on some UniPhier reference boards.
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Say Y to use the on-board UART, Ether, LED devices.
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config CMD_PINMON
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bool "Enable boot mode pins monitor command"
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default y
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help
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The command "pinmon" shows the state of the boot mode pins.
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The boot mode pins are latched when the system reset is deasserted
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and determine which device the system should load a boot image from.
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config CMD_DDRPHY_DUMP
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bool "Enable dump command of DDR PHY parameters"
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depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || ARCH_UNIPHIER_SLD8
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default y
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help
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The command "ddrphy" shows the resulting parameters of DDR PHY
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training; it is useful for the evaluation of DDR PHY training.
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config CMD_DDRMPHY_DUMP
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bool "Enable dump command of DDR Multi PHY parameters"
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depends on ARCH_UNIPHIER_PXS2 || ARCH_UNIPHIER_LD6B
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default y
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help
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The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
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training; it is useful for the evaluation of DDR Multi PHY training.
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endif
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