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![Nobuhiro Iwamatsu](/assets/img/avatar_default.png)
Renesas R8A7740 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
288 lines
5.3 KiB
C
288 lines
5.3 KiB
C
/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_R8A7740_H
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#define __ASM_ARCH_R8A7740_H
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/*
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* R8A7740 I/O Addresses
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*/
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#define MERAM_BASE 0xE5580000
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#define DDRP_BASE 0xC12A0000
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#define HPB_BASE 0xE6000000
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#define RWDT0_BASE 0xE6020000
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#define RWDT1_BASE 0xE6030000
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#define GPIO_BASE 0xE6050000
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#define CMT1_BASE 0xE6138000
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#define CPG_BASE 0xE6150000
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#define SYSC_BASE 0xE6180000
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#define SDHI0_BASE 0xE6850000
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#define SDHI1_BASE 0xE6860000
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#define MMCIF_BASE 0xE6BD0000
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#define SCIF5_BASE 0xE6CB0000
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#define SCIF6_BASE 0xE6CC0000
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#define DBSC_BASE 0xFE400000
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#define BSC_BASE 0xFEC10000
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#define I2C0_BASE 0xFFF20000
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#define I2C1_BASE 0xE6C20000
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#define TMU_BASE 0xFFF80000
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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/* RWDT */
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struct r8a7740_rwdt {
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u16 rwtcnt0; /* 0x00 */
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u16 dummy0; /* 0x02 */
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u16 rwtcsra0; /* 0x04 */
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u16 dummy1; /* 0x06 */
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u16 rwtcsrb0; /* 0x08 */
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u16 dummy2; /* 0x0A */
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};
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/* HPB Semaphore Control Registers */
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struct r8a7740_hpb {
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u32 hpbctrl0;
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u32 hpbctrl1;
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u32 hpbctrl2;
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u32 cccr;
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u32 dummy0; /* 0x20 */
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u32 hpbctrl4;
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u32 hpbctrl5;
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};
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/* CPG */
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struct r8a7740_cpg {
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u32 frqcra;
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u32 frqcrb;
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u32 vclkcr1;
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u32 vclkcr2;
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u32 fmsickcr;
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u32 fmsockcr;
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u32 fsiackcr;
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u32 dummy0; /* 0x1c */
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u32 rtstbcr;
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u32 systbcr;
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u32 pllc01cr;
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u32 pllc2cr;
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u32 mstpsr0;
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u32 dummy1; /* 0x34 */
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u32 mstpsr1;
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u32 mstpsr5;
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u32 mstpsr2;
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u32 dummy2; /* 0x44 */
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u32 mstpsr3;
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u32 mstpsr4;
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u32 dummy3; /* 0x50 */
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u32 astat;
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u32 dummy4[4]; /* 0x58 .. 0x64 */
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u32 ztrckcr;
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u32 dummy5[5]; /* 0x6c .. 0x7c */
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u32 subckcr;
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u32 spuckcr;
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u32 vouckcr;
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u32 usbckcr;
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u32 dummy6[3]; /* 0x90 .. 0x98 */
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u32 stprckcr;
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u32 srcr0;
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u32 dummy7; /* 0xa4 */
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u32 srcr1;
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u32 dummy8; /* 0xac */
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u32 srcr2;
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u32 dummy9; /* 0xb4 */
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u32 srcr3;
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u32 srcr4;
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u32 dummy10; /* 0xc0 */
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u32 srcr5;
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u32 pllc01stpcr;
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u32 dummy11[5]; /* 0xcc .. 0xdc */
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u32 frqcrc;
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u32 frqcrd;
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u32 dummy12[10]; /* 0xe8 .. 0x10c */
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u32 rmstpcr0;
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u32 rmstpcr1;
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u32 rmstpcr2;
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u32 rmstpcr3;
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u32 rmstpcr4;
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u32 rmstpcr5;
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u32 dummy13[2]; /* 0x128 .. 0x12c */
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u32 smstpcr0;
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u32 smstpcr1;
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u32 smstpcr2;
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u32 smstpcr3;
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u32 smstpcr4;
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u32 smstpcr5;
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};
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/* BSC */
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struct r8a7740_bsc {
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u32 cmncr;
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u32 cs0bcr;
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u32 cs2bcr;
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u32 dummy0; /* 0x0c */
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u32 cs4bcr;
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u32 cs5abcr;
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u32 cs5bbcr;
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u32 cs6abcr;
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u32 dummy1; /* 0x20 */
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u32 cs0wcr;
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u32 cs2wcr;
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u32 dummy2; /* 0x2c */
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u32 cs4wcr;
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u32 cs5awcr;
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u32 cs5bwcr;
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u32 cs6awcr;
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u32 dummy3[5]; /* 0x40 .. 0x50 */
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u32 rbwtcnt;
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u32 busycr;
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u32 dummy4[5]; /* 0x5c .. 0x6c */
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u32 bromtimcr;
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u32 dummy5[7]; /* 0x74 .. 0x8c */
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u32 bptcr00;
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u32 bptcr01;
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u32 bptcr02;
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u32 bptcr03;
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u32 bptcr04;
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u32 bptcr05;
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u32 bptcr06;
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u32 bptcr07;
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u32 bptcr08;
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u32 bptcr09;
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u32 bptcr10;
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u32 bptcr11;
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u32 bptcr12;
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u32 bptcr13;
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u32 bptcr14;
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u32 bptcr15;
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u32 bptcr16;
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u32 bptcr17;
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u32 bptcr18;
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u32 bptcr19;
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u32 bptcr20;
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u32 bptcr21;
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u32 bptcr22;
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u32 bptcr23;
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u32 bptcr24;
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u32 bptcr25;
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u32 bptcr26;
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u32 bptcr27;
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u32 bptcr28;
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u32 bptcr29;
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u32 bptcr30;
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u32 bptcr31;
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u32 bswcr;
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u32 dummy6[68]; /* 0x114 .. 0x220 */
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u32 cs0wcr2;
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u32 cs2wcr2;
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u32 dummy7; /* 0x22c */
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u32 cs4wcr2;
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};
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#define CS0WCR2 0xFEC10224
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#define CS2WCR2 0xFEC10228
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#define CS4WCR2 0xFEC10230
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/* DDRP */
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struct r8a7740_ddrp {
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u32 funcctrl;
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u32 dllctrl;
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u32 zqcalctrl;
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u32 zqodtctrl;
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u32 rdctrl;
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u32 rdtmg;
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u32 fifoinit;
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u32 outctrl;
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u32 dummy0[50]; /* 0x20 .. 0xe4 */
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u32 dqcalofs1;
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u32 dqcalofs2;
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u32 dummy1[2]; /* 0xf0 .. 0xf4 */
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u32 dqcalexp;
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};
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#define DDRPNCNT 0xE605803C
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#define DDRVREFCNT 0xE61500EC
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/* DBSC */
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struct r8a7740_dbsc {
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u32 dummy0;
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u32 dbsvcr;
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u32 dbstate0;
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u32 dbstate1;
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u32 dbacen;
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u32 dbrfen;
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u32 dbcmd;
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u32 dbwait;
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u32 dbkind;
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u32 dbconf0;
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u32 dummy1[2]; /* 0x28 .. 0x2c */
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u32 dbphytype;
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u32 dummy2[3]; /* 0x34 .. 0x3c */
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u32 dbtr0;
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u32 dbtr1;
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u32 dbtr2;
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u32 dummy3; /* 0x4c */
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u32 dbtr3;
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u32 dbtr4;
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u32 dbtr5;
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u32 dbtr6;
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u32 dbtr7;
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u32 dbtr8;
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u32 dbtr9;
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u32 dbtr10;
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u32 dbtr11;
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u32 dbtr12;
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u32 dbtr13;
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u32 dbtr14;
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u32 dbtr15;
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u32 dbtr16;
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u32 dbtr17;
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u32 dbtr18;
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u32 dbtr19;
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u32 dummy4[7]; /* 0x94 .. 0xac */
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u32 dbbl;
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u32 dummy5[3]; /* 0xb4 .. 0xbc */
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u32 dbadj0;
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u32 dbadj1;
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u32 dbadj2;
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u32 dummy6[5]; /* 0xcc .. 0xdc */
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u32 dbrfcnf0;
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u32 dbrfcnf1;
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u32 dbrfcnf2;
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u32 dbrfcnf3;
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u32 dummy7; /* 0xf0 */
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u32 dbcalcnf;
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u32 dbcaltr;
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u32 dummy8; /* 0xfc */;
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u32 dbrnk0;
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u32 dummy9[31]; /* 0x104 .. 0x17C */
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u32 dbpdncnf;
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u32 dummy10[7]; /* 0x184 .. 0x19C */
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u32 dbmrrdr;
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u32 dummy11[39]; /* 0x1A4 .. 0x23C */
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u32 dbdfistat;
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u32 dbdficnt;
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u32 dummy12[46]; /* 0x248 .. 0x2FC */
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u32 dbbs0cnt0;
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u32 dbbs0cnt1;
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};
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#endif
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#endif /* __ASM_ARCH_R8A7740_H */
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