mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 06:43:28 +09:00
4909b89ec7
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
||
---|---|---|
.. | ||
fsl-layerscape | ||
hisilicon | ||
s32v234 | ||
zynqmp | ||
cache_v8.c | ||
cache.S | ||
config.mk | ||
cpu-dt.c | ||
cpu.c | ||
exceptions.S | ||
fwcall.c | ||
generic_timer.c | ||
Kconfig | ||
linux-kernel-image-header-vars.h | ||
lowlevel_init.S | ||
Makefile | ||
psci.S | ||
sec_firmware_asm.S | ||
sec_firmware.c | ||
smccc-call.S | ||
spin_table_v8.S | ||
spin_table.c | ||
start.S | ||
tlb.S | ||
transition.S | ||
u-boot-spl.lds | ||
u-boot.lds |