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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 00:48:52 +09:00
![Stefan Roese](/assets/img/avatar_default.png)
This patch introduces a weak default function for post_hotkey_pressed(), returning 0, for boards without hotkey support. The long-running tests won't be started on those boards. This default function was implemented in many board directories. By implementing this weak default we can remove all those duplicate versions. Boards with hotkey support, can override this weak default function by defining one in their board specific code. Signed-off-by: Stefan Roese <sr@denx.de>
295 lines
7.6 KiB
C
295 lines
7.6 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Keith Outwater, keith_outwater@mvis.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <virtex2.h>
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/8xx_immap.h>
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#include "beeper.h"
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#include "fpga.h"
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#include "ioport.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_STATUS_LED
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#include <status_led.h>
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#endif
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#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
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#include <net.h>
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#endif
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#if 0
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#define GEN860T_DEBUG
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#endif
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#ifdef GEN860T_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/*
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* The following UPM init tables were generated automatically by
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* Motorola's MCUINIT program. See the README file for UPM to
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* SDRAM pin assignments if you want to type this data into
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* MCUINIT in order to reverse engineer the waveforms.
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*/
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/*
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* UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
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* (UPMA) and Virtex FPGA SelectMap interface (UPMB).
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* NOTE that unused areas of the table are used to hold NOP, precharge
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* and mode register set sequences.
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*
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*/
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#define UPMA_NOP_ADDR 0x5
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#define UPMA_PRECHARGE_ADDR 0x6
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#define UPMA_MRS_ADDR 0x12
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#define UPM_SINGLE_READ_ADDR 0x00
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#define UPM_BURST_READ_ADDR 0x08
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#define UPM_SINGLE_WRITE_ADDR 0x18
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#define UPM_BURST_WRITE_ADDR 0x20
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#define UPM_REFRESH_ADDR 0x30
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const uint sdram_upm_table[] = {
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/* single read (offset 0x00 in upm ram) */
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0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
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0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
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/* burst read (offset 0x08 in upm ram) */
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0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
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0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
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0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
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0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
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/* single write (offset 0x18 in upm ram) */
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0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* burst write (offset 0x20 in upm ram) */
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0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
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0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* refresh (offset 0x30 in upm ram) */
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0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
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0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* exception (offset 0x3C in upm ram) */
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};
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const uint selectmap_upm_table[] = {
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/* single read (offset 0x00 in upm ram) */
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0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
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0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
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/* burst read (offset 0x08 in upm ram) */
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0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* single write (offset 0x18 in upm ram) */
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0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* burst write (offset 0x20 in upm ram) */
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0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* refresh (offset 0x30 in upm ram) */
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0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/* exception (offset 0x3C in upm ram) */
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0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
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};
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/*
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* Check board identity. Always successful (gives information only)
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*/
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int checkboard (void)
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{
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char *s;
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char buf[64];
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int i;
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i = getenv_r ("board_id", buf, sizeof (buf));
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s = (i > 0) ? buf : NULL;
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if (s) {
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printf ("%s ", s);
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} else {
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printf ("<unknown> ");
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}
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i = getenv_r ("serial#", buf, sizeof (buf));
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s = (i > 0) ? buf : NULL;
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if (s) {
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printf ("S/N %s\n", s);
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} else {
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printf ("S/N <unknown>\n");
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}
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printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
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printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
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return (0);
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}
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/*
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* Initialize SDRAM
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*/
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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upmconfig (UPMA,
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(uint *) sdram_upm_table,
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sizeof (sdram_upm_table) / sizeof (uint)
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);
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/*
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* Setup MAMR register
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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/*
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* Map CS1* to SDRAM bank
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*/
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memctl->memc_or1 = CONFIG_SYS_OR1;
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memctl->memc_br1 = CONFIG_SYS_BR1;
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/*
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* Perform SDRAM initialization sequence:
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* 1. Apply at least one NOP command
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* 2. 100 uS delay (JEDEC standard says 200 uS)
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* 3. Issue 4 precharge commands
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* 4. Perform two refresh cycles
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* 5. Program mode register
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*
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* Program SDRAM for standard operation, sequential burst, burst length
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* of 4, CAS latency of 2.
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*/
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memctl->memc_mar = 0x00000000;
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memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
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MCR_MLCF (0) | UPMA_NOP_ADDR;
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udelay (200);
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memctl->memc_mar = 0x00000000;
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memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
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MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
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memctl->memc_mar = 0x00000000;
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memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
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MCR_MLCF (2) | UPM_REFRESH_ADDR;
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memctl->memc_mar = 0x00000088;
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memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
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MCR_MLCF (1) | UPMA_MRS_ADDR;
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memctl->memc_mar = 0x00000000;
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memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
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MCR_MLCF (0) | UPMA_NOP_ADDR;
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/*
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* Enable refresh
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*/
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memctl->memc_mamr |= MAMR_PTAE;
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return (SDRAM_SIZE);
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}
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/*
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* Disk On Chip (DOC) Millenium initialization.
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* The DOC lives in the CS2* space
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*/
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#if defined(CONFIG_CMD_DOC)
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void doc_init (void)
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{
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printf ("Probing at 0x%.8x: ", DOC_BASE);
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doc_probe (DOC_BASE);
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}
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#endif
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/*
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* Miscellaneous intialization
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*/
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int misc_init_r (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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/*
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* Set up UPMB to handle the Virtex FPGA SelectMap interface
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*/
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upmconfig (UPMB, (uint *) selectmap_upm_table,
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sizeof (selectmap_upm_table) / sizeof (uint));
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memctl->memc_mbmr = 0x0;
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config_mpc8xx_ioports (immr);
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#if defined(CONFIG_CMD_MII)
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mii_init ();
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#endif
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#if defined(CONFIG_FPGA)
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gen860t_init_fpga ();
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#endif
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return 0;
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}
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/*
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* Final init hook before entering command loop.
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*/
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int last_stage_init (void)
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{
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#if !defined(CONFIG_SC)
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char buf[256];
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int i;
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/*
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* Turn the beeper volume all the way down in case this is a warm boot.
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*/
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set_beeper_volume (-64);
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init_beeper ();
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/*
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* Read the environment to see what to do with the beeper
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*/
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i = getenv_r ("beeper", buf, sizeof (buf));
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if (i > 0) {
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do_beeper (buf);
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}
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#endif
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return 0;
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}
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/*
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* Stub to make POST code happy. Can't self-poweroff, so just hang.
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*/
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void board_poweroff (void)
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{
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puts ("### Please power off the board ###\n");
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while (1);
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}
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