mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-11 07:13:21 +09:00
![Kumar Gala](/assets/img/avatar_default.png)
Since board_hwconfig & cpu_hwconfig are defined as weak and dont have a default value they will get put into the BSS if they aren't defined elsewhere. This is problematic as we try to utilize hwconfig before we've relocated and thus BSS isn't setup. Instead of giving dummy values in the board files that utilize this feature, we can just initialize the variables to an empty string and thus move them out of the BSS if they aren't defined elsewhere. Also made board_hwconfig & cpu_hwconfig arrays to reduce size associated with string pointers vs arrays. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
320 lines
7.1 KiB
C
320 lines
7.1 KiB
C
/*
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* Copyright 2006, 2007, 2010 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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phys_size_t fixed_sdram(void);
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int board_early_init_f(void)
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{
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return 0;
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}
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int checkboard(void)
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{
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u8 vboot;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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vboot = in_8(pixis_base + PIXIS_VBOOT);
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if (vboot & PIXIS_VBOOT_FMAP)
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printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
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else
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puts ("Promjet\n");
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#ifdef CONFIG_PHYS_64BIT
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printf (" 36-bit physical address map\n");
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#endif
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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setup_ddr_bat(dram_size);
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t
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fixed_sdram(void)
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{
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#if !defined(CONFIG_SYS_RAMBOOT)
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
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ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000008D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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#endif
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asm("sync; isync");
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udelay(500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif /* CONFIG_PCIE2 */
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int first_free_busno = 0;
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void pci_init_board(void)
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{
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struct fsl_pci_info pci_info[2];
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int pcie_ep;
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int num = 0;
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#ifdef CONFIG_PCIE1
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint devdisr = in_be32(&gur->devdisr);
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uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
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>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
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int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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*/
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in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
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+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
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} else {
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puts("PCIE1: disabled\n");
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}
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#else
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puts("PCIE1: disabled\n");
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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#else
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puts("PCIE2: disabled\n");
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#endif /* CONFIG_PCIE2 */
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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int off;
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u64 *tmp;
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u32 *addrcells;
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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/*
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* Warn if it looks like the device tree doesn't match u-boot.
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* This is just an estimation, based on the location of CCSR,
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* which is defined by the "reg" property in the soc node.
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*/
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off = fdt_path_offset(blob, "/soc8641");
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addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
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tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
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if (tmp) {
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u64 addr;
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if (addrcells && (*addrcells == 1))
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addr = *(u32 *)tmp;
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else
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addr = *tmp;
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if (addr != CONFIG_SYS_CCSRBAR_PHYS)
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printf("WARNING: The CCSRBAR address in your .dts "
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"does not match the address of the CCSR "
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"in u-boot. This means your .dts might "
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"be old.\n");
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}
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}
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#endif
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/*
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* get_board_sys_clk
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* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
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*/
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unsigned long
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get_board_sys_clk(ulong dummy)
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{
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u8 i, go_bit, rd_clks;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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go_bit = in_8(pixis_base + PIXIS_VCTL);
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go_bit &= 0x01;
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rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
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rd_clks &= 0x1C;
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/*
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* Only if both go bit and the SCLK bit in VCFGEN0 are set
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* should we be using the AUX register. Remember, we also set the
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* GO bit to boot from the alternate bank on the on-board flash
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*/
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if (go_bit) {
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if (rd_clks == 0x1c)
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i = in_8(pixis_base + PIXIS_AUX);
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else
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i = in_8(pixis_base + PIXIS_SPD);
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} else {
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i = in_8(pixis_base + PIXIS_SPD);
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}
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33000000;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66000000;
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break;
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case 4:
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val = 83000000;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 134000000;
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break;
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case 7:
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val = 166000000;
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break;
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}
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return val;
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}
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int board_eth_init(bd_t *bis)
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{
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/* Initialize TSECs */
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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}
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void board_reset(void)
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{
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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out_8(pixis_base + PIXIS_RST, 0);
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while (1)
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;
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}
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#ifdef CONFIG_MP
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extern void cpu_mp_lmb_reserve(struct lmb *lmb);
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void board_lmb_reserve(struct lmb *lmb)
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{
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cpu_mp_lmb_reserve(lmb);
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}
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#endif
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