mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
ceec08f50b
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. This is controlled by pcf gpio line. Add appropriate mode-gpios DT entry so that driver can select the required slave. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
685 lines
16 KiB
Plaintext
685 lines
16 KiB
Plaintext
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "TI DRA722";
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
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chosen {
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stdout-path = &uart1;
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tick-timer = &timer2;
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>; /* 1024 MB */
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};
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aliases {
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display0 = &hdmi0;
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};
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evm_3v3: fixedregulator-evm_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb2: extcon_usb2 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
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};
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hdmi0: connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tpd12s015_out>;
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};
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};
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};
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tpd12s015: encoder {
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compatible = "ti,tpd12s015";
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pinctrl-names = "default";
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pinctrl-0 = <&tpd12s015_pins>;
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gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
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<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
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<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpd12s015_in: endpoint {
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remote-endpoint = <&hdmi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tpd12s015_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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};
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&dra7_pmx_core {
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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>;
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};
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i2c5_pins: pinmux_i2c5_pins {
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pinctrl-single,pins = <
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0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
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0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
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>;
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};
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nand_default: nand_default {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
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0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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>;
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};
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usb2_pins: pinmux_usb2_pins {
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pinctrl-single,pins = <
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0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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tps65917_pins_default: tps65917_pins_default {
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pinctrl-single,pins = <
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0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
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>;
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};
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mmc1_pins_default: mmc1_pins_default {
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pinctrl-single,pins = <
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0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
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0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
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0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
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0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
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0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
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0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
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0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
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>;
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};
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mmc2_pins_default: mmc2_pins_default {
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pinctrl-single,pins = <
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0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
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0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
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0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
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0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
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0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
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0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
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0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
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0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
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0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
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0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
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>;
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};
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
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0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
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>;
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};
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qspi1_pins: pinmux_qspi1_pins {
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pinctrl-single,pins = <
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0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
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0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
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0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
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0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
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0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
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0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
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0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
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>;
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};
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hdmi_pins: pinmux_hdmi_pins {
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pinctrl-single,pins = <
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0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
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0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
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>;
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};
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tpd12s015_pins: pinmux_tpd12s015_pins {
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pinctrl-single,pins = <
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0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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tps65917: tps65917@58 {
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compatible = "ti,tps65917";
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reg = <0x58>;
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pinctrl-names = "default";
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pinctrl-0 = <&tps65917_pins_default>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,system-power-controller;
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tps65917_pmic {
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compatible = "ti,tps65917-pmic";
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regulators {
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smps1_reg: smps1 {
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/* VDD_MPU */
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regulator-name = "smps1";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps2_reg: smps2 {
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/* VDD_CORE */
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regulator-name = "smps2";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1060000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps3_reg: smps3 {
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/* VDD_GPU IVA DSPEVE */
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regulator-name = "smps3";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps4_reg: smps4 {
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/* VDDS1V8 */
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regulator-name = "smps4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps5_reg: smps5 {
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/* VDD_DDR */
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regulator-name = "smps5";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: ldo1 {
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/* LDO1_OUT --> SDIO */
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo2_reg: ldo2 {
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/* LDO2_OUT --> TP1017 (UNUSED) */
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regulator-name = "ldo2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo3_reg: ldo3 {
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/* VDDA_1V8_PHY */
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5_reg: ldo5 {
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/* VDDA_1V8_PLL */
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regulator-name = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo4_reg: ldo4 {
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/* VDDA_3V_USB: VDDA_USBHS33 */
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regulator-name = "ldo4";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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};
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tps65917_power_button {
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compatible = "ti,palmas-pwrbutton";
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interrupt-parent = <&tps65917>;
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interrupts = <1 IRQ_TYPE_NONE>;
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wakeup-source;
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ti,palmas-long-press-seconds = <6>;
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};
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};
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pcf_gpio_21: gpio@21 {
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compatible = "ti,pcf8575";
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reg = <0x21>;
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lines-initial-states = <0x1408>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio6>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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u-boot,i2c-offset-len = <0>;
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};
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};
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&i2c5 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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clock-frequency = <400000>;
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pcf_hdmi: pcf8575@26 {
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compatible = "nxp,pcf8575";
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reg = <0x26>;
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gpio-controller;
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#gpio-cells = <2>;
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/*
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* initial state is used here to keep the mdio interface
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* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
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* VIN2_S0 driven high otherwise Ethernet stops working
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* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
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*/
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lines-initial-states = <0x0f2b>;
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u-boot,i2c-offset-len = <0>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_default>;
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ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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/* To use NAND, DIP switch SW5 must be set like so:
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* SW5.1 (NAND_SELn) = ON (LOW)
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* SW5.9 (GPMC_WPN) = OFF (HIGH)
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*/
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reg = <0 0 4>; /* device IO registers */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <80>;
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gpmc,cs-wr-off-ns = <80>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <60>;
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gpmc,adv-wr-off-ns = <60>;
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gpmc,we-on-ns = <10>;
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gpmc,we-off-ns = <50>;
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gpmc,oe-on-ns = <4>;
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gpmc,oe-off-ns = <40>;
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gpmc,access-ns = <40>;
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gpmc,wr-access-ns = <80>;
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gpmc,rd-cycle-ns = <80>;
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gpmc,wr-cycle-ns = <80>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot-spl-os";
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reg = <0x00080000 0x00040000>;
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};
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partition@5 {
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label = "NAND.u-boot";
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reg = <0x000c0000 0x00100000>;
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};
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partition@6 {
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label = "NAND.u-boot-env";
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|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
phy-supply = <&ldo4_reg>;
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
phy-supply = <&ldo4_reg>;
|
|
};
|
|
|
|
&omap_dwc3_1 {
|
|
extcon = <&extcon_usb1>;
|
|
};
|
|
|
|
&omap_dwc3_2 {
|
|
extcon = <&extcon_usb2>;
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb1_pins>;
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb2_pins>;
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins_default>;
|
|
|
|
vmmc-supply = <&ldo1_reg>;
|
|
bus-width = <4>;
|
|
/*
|
|
* SDCD signal is not being used here - using the fact that GPIO mode
|
|
* is a viable alternative
|
|
*/
|
|
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
&mmc2 {
|
|
/* SW5-3 in ON position */
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins_default>;
|
|
|
|
vmmc-supply = <&evm_3v3>;
|
|
bus-width = <8>;
|
|
ti,non-removable;
|
|
};
|
|
|
|
&dra7_pmx_core {
|
|
cpsw_default: cpsw_default {
|
|
pinctrl-single,pins = <
|
|
/* Slave 2 */
|
|
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
|
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
|
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
|
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
|
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
|
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
|
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
|
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
|
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
|
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
|
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
|
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
|
>;
|
|
|
|
};
|
|
|
|
cpsw_sleep: cpsw_sleep {
|
|
pinctrl-single,pins = <
|
|
/* Slave 2 */
|
|
0x198 (MUX_MODE15)
|
|
0x19c (MUX_MODE15)
|
|
0x1a0 (MUX_MODE15)
|
|
0x1a4 (MUX_MODE15)
|
|
0x1a8 (MUX_MODE15)
|
|
0x1ac (MUX_MODE15)
|
|
0x1b0 (MUX_MODE15)
|
|
0x1b4 (MUX_MODE15)
|
|
0x1b8 (MUX_MODE15)
|
|
0x1bc (MUX_MODE15)
|
|
0x1c0 (MUX_MODE15)
|
|
0x1c4 (MUX_MODE15)
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_default: davinci_mdio_default {
|
|
pinctrl-single,pins = <
|
|
/* MDIO */
|
|
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
|
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_sleep: davinci_mdio_sleep {
|
|
pinctrl-single,pins = <
|
|
0x23c (MUX_MODE15)
|
|
0x240 (MUX_MODE15)
|
|
>;
|
|
};
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <3>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
};
|
|
|
|
&dcan1 {
|
|
status = "ok";
|
|
pinctrl-names = "default", "sleep", "active";
|
|
pinctrl-0 = <&dcan1_pins_sleep>;
|
|
pinctrl-1 = <&dcan1_pins_sleep>;
|
|
pinctrl-2 = <&dcan1_pins_default>;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi1_pins>;
|
|
|
|
spi-max-frequency = <76800000>;
|
|
m25p80@0 {
|
|
compatible = "s25fl256s1","spi-flash";
|
|
spi-max-frequency = <64000000>;
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first four physical blocks
|
|
* for a valid file to boot and the flash here is
|
|
* 64KiB block size.
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.SPL";
|
|
reg = <0x00000000 0x000010000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.SPL.backup1";
|
|
reg = <0x00010000 0x00010000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.SPL.backup2";
|
|
reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00080000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x001c0000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x001d0000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001e0000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009e0000 0x01620000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
|
|
vdda_video-supply = <&ldo5_reg>;
|
|
};
|
|
|
|
&hdmi {
|
|
status = "ok";
|
|
vdda-supply = <&ldo3_reg>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_pins>;
|
|
|
|
port {
|
|
hdmi_out: endpoint {
|
|
remote-endpoint = <&tpd12s015_in>;
|
|
};
|
|
};
|
|
};
|