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![Steve Kipisz](/assets/img/avatar_default.png)
The AM572x-IDK board (Industrial Dev Kit) is a board based on TI's AM5728x SOC which has a dual core 1.5GHz A15 processor. This board is a development platform for the Industrial market with: - 2GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - PRU-ICSS - uSD - 16GB eMMC - CAN - RS-485 - PCIe - USB3.0 - Video Input Port - Industrial IO port and expansion connector The link to the data sheet and TRM can be found here: http://www.ti.com/product/AM5728 NOTE: DT support is still pending upstream kernel acceptance but we should be able to get the base system support with this patch. Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
685 lines
15 KiB
C
685 lines
15 KiB
C
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Author: Felipe Balbi <balbi@ti.com>
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*
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* Based on board/ti/dra7xx/evm.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <palmas.h>
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#include <sata.h>
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#include <usb.h>
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#include <asm/omap_common.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dra7xx_iodelay.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sata.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/omap.h>
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#include <environment.h>
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#include <usb.h>
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#include <linux/usb/gadget.h>
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#include <dwc3-uboot.h>
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#include <dwc3-omap-uboot.h>
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#include <ti-usb-phy-uboot.h>
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#include "../common/board_detect.h"
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#include "mux_data.h"
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#define board_is_x15() board_ti_is("BBRDX15_")
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#define board_is_am572x_evm() board_ti_is("AM572PM_")
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#define board_is_am572x_idk() board_ti_is("AM572IDK")
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#ifdef CONFIG_DRIVER_TI_CPSW
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#include <cpsw.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO 7_11 */
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#define GPIO_DDR_VTT_EN 203
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#define SYSINFO_BOARD_NAME_MAX_LEN 45
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const struct omap_sysinfo sysinfo = {
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"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
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};
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static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
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.dmm_lisa_map_3 = 0x80740300,
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.is_ma_present = 0x1
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};
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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*dmm_lisa_regs = &beagle_x15_lisa_regs;
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}
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static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xcccf36ab,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x409f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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/* Ext phy ctrl regs 1-35 */
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static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xcccf36b3,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x407f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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switch (emif_nr) {
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case 1:
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*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
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break;
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case 2:
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*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
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break;
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}
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}
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void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
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{
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switch (emif_nr) {
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case 1:
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*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
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*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
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break;
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case 2:
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*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
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*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
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break;
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}
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}
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struct vcores_data beagle_x15_volts = {
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.mpu.value = VDD_MPU_DRA752,
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.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
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.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.mpu.addr = TPS659038_REG_ADDR_SMPS12,
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.mpu.pmic = &tps659038,
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.eve.value = VDD_EVE_DRA752,
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.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
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.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.eve.addr = TPS659038_REG_ADDR_SMPS45,
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.eve.pmic = &tps659038,
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.gpu.value = VDD_GPU_DRA752,
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.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
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.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.gpu.addr = TPS659038_REG_ADDR_SMPS45,
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.gpu.pmic = &tps659038,
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.core.value = VDD_CORE_DRA752,
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.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
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.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.core.addr = TPS659038_REG_ADDR_SMPS6,
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.core.pmic = &tps659038,
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.iva.value = VDD_IVA_DRA752,
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.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
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.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.iva.addr = TPS659038_REG_ADDR_SMPS45,
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.iva.pmic = &tps659038,
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};
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#ifdef CONFIG_SPL_BUILD
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/* No env to setup for SPL */
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static inline void setup_board_eeprom_env(void) { }
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/* Override function to read eeprom information */
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void do_board_detect(void)
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{
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int rc;
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rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
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CONFIG_EEPROM_CHIP_ADDRESS);
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if (rc)
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printf("ti_i2c_eeprom_init failed %d\n", rc);
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}
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#else /* CONFIG_SPL_BUILD */
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/* Override function to read eeprom information: actual i2c read done by SPL*/
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void do_board_detect(void)
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{
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char *bname = NULL;
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int rc;
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rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
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CONFIG_EEPROM_CHIP_ADDRESS);
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if (rc)
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printf("ti_i2c_eeprom_init failed %d\n", rc);
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if (board_is_x15())
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bname = "BeagleBoard X15";
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else if (board_is_am572x_evm())
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bname = "AM572x EVM";
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else if (board_is_am572x_idk())
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bname = "AM572x IDK";
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if (bname)
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snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
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"Board: %s REV %s\n", bname, board_ti_get_rev());
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}
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static void setup_board_eeprom_env(void)
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{
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char *name = "beagle_x15";
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int rc;
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rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
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CONFIG_EEPROM_CHIP_ADDRESS);
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if (rc)
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goto invalid_eeprom;
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if (board_is_am572x_evm())
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name = "am57xx_evm";
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else if (board_is_am572x_idk())
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name = "am572x_idk";
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else
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printf("Unidentified board claims %s in eeprom header\n",
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board_ti_get_name());
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invalid_eeprom:
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set_board_info_env(name);
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}
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#endif /* CONFIG_SPL_BUILD */
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void hw_data_init(void)
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{
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*prcm = &dra7xx_prcm;
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*dplls_data = &dra7xx_dplls;
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*omap_vcores = &beagle_x15_volts;
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*ctrl = &dra7xx_ctrl;
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}
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
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return 0;
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}
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int board_late_init(void)
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{
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setup_board_eeprom_env();
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/*
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* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
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* This is the POWERHOLD-in-Low behavior.
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*/
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palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
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return 0;
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}
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void set_muxconf_regs(void)
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{
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do_set_mux32((*ctrl)->control_padconf_core_base,
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early_padconf, ARRAY_SIZE(early_padconf));
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}
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#ifdef CONFIG_IODELAY_RECALIBRATION
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void recalibrate_iodelay(void)
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{
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const struct pad_conf_entry *pconf;
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const struct iodelay_cfg_entry *iod;
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int pconf_sz, iod_sz;
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if (board_is_am572x_idk()) {
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pconf = core_padconf_array_essential_am572x_idk;
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pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
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iod = iodelay_cfg_array_am572x_idk;
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iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
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} else {
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/* Common for X15/GPEVM */
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pconf = core_padconf_array_essential_x15;
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pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
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iod = iodelay_cfg_array_x15;
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iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
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}
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__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
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}
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#endif
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0, 0, 0, -1, -1);
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omap_mmc_init(1, 0, 0, -1, -1);
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return 0;
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}
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#endif
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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env_init();
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env_relocate_spec();
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if (getenv_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device usb_otg_ss1 = {
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.maximum_speed = USB_SPEED_SUPER,
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.base = DRA7_USB_OTG_SS1_BASE,
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.tx_fifo_resize = false,
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.index = 0,
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};
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static struct dwc3_omap_device usb_otg_ss1_glue = {
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.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
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.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
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.index = 0,
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};
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static struct ti_usb_phy_device usb_phy1_device = {
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.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
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.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
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.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
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.index = 0,
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};
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static struct dwc3_device usb_otg_ss2 = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = DRA7_USB_OTG_SS2_BASE,
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.tx_fifo_resize = false,
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.index = 1,
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};
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static struct dwc3_omap_device usb_otg_ss2_glue = {
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.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
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.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
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.index = 1,
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};
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static struct ti_usb_phy_device usb_phy2_device = {
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.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
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.index = 1,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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enable_usb_clocks(index);
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switch (index) {
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case 0:
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if (init == USB_INIT_DEVICE) {
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printf("port %d can't be used as device\n", index);
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disable_usb_clocks(index);
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return -EINVAL;
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} else {
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usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
|
|
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
|
|
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
|
|
OTG_SS_CLKCTRL_MODULEMODE_HW |
|
|
OPTFCLKEN_REFCLK960M);
|
|
}
|
|
|
|
ti_usb_phy_uboot_init(&usb_phy1_device);
|
|
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
|
|
dwc3_uboot_init(&usb_otg_ss1);
|
|
break;
|
|
case 1:
|
|
if (init == USB_INIT_DEVICE) {
|
|
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
|
|
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
|
|
} else {
|
|
printf("port %d can't be used as host\n", index);
|
|
disable_usb_clocks(index);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ti_usb_phy_uboot_init(&usb_phy2_device);
|
|
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
|
|
dwc3_uboot_init(&usb_otg_ss2);
|
|
break;
|
|
default:
|
|
printf("Invalid Controller Index\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_usb_cleanup(int index, enum usb_init_type init)
|
|
{
|
|
switch (index) {
|
|
case 0:
|
|
case 1:
|
|
ti_usb_phy_uboot_exit(index);
|
|
dwc3_uboot_exit(index);
|
|
dwc3_omap_uboot_exit(index);
|
|
break;
|
|
default:
|
|
printf("Invalid Controller Index\n");
|
|
}
|
|
disable_usb_clocks(index);
|
|
return 0;
|
|
}
|
|
|
|
int usb_gadget_handle_interrupts(int index)
|
|
{
|
|
u32 status;
|
|
|
|
status = dwc3_omap_uboot_interrupt_status(index);
|
|
if (status)
|
|
dwc3_uboot_handle_interrupt(index);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DRIVER_TI_CPSW
|
|
|
|
/* Delay value to add to calibrated value */
|
|
#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
|
|
#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
|
|
#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
|
|
#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
|
|
#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
|
|
#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
|
|
#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
|
|
#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
|
|
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
|
|
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
|
|
|
|
static void cpsw_control(int enabled)
|
|
{
|
|
/* VTP can be added here */
|
|
}
|
|
|
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
|
{
|
|
.slave_reg_ofs = 0x208,
|
|
.sliver_reg_ofs = 0xd80,
|
|
.phy_addr = 1,
|
|
},
|
|
{
|
|
.slave_reg_ofs = 0x308,
|
|
.sliver_reg_ofs = 0xdc0,
|
|
.phy_addr = 2,
|
|
},
|
|
};
|
|
|
|
static struct cpsw_platform_data cpsw_data = {
|
|
.mdio_base = CPSW_MDIO_BASE,
|
|
.cpsw_base = CPSW_BASE,
|
|
.mdio_div = 0xff,
|
|
.channels = 8,
|
|
.cpdma_reg_ofs = 0x800,
|
|
.slaves = 1,
|
|
.slave_data = cpsw_slaves,
|
|
.ale_reg_ofs = 0xd00,
|
|
.ale_entries = 1024,
|
|
.host_port_reg_ofs = 0x108,
|
|
.hw_stats_reg_ofs = 0x900,
|
|
.bd_ram_ofs = 0x2000,
|
|
.mac_control = (1 << 5),
|
|
.control = cpsw_control,
|
|
.host_port_num = 0,
|
|
.version = CPSW_CTRL_VERSION_2,
|
|
};
|
|
|
|
static u64 mac_to_u64(u8 mac[6])
|
|
{
|
|
int i;
|
|
u64 addr = 0;
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
addr <<= 8;
|
|
addr |= mac[i];
|
|
}
|
|
|
|
return addr;
|
|
}
|
|
|
|
static void u64_to_mac(u64 addr, u8 mac[6])
|
|
{
|
|
mac[5] = addr;
|
|
mac[4] = addr >> 8;
|
|
mac[3] = addr >> 16;
|
|
mac[2] = addr >> 24;
|
|
mac[1] = addr >> 32;
|
|
mac[0] = addr >> 40;
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int ret;
|
|
uint8_t mac_addr[6];
|
|
uint32_t mac_hi, mac_lo;
|
|
uint32_t ctrl_val;
|
|
int i;
|
|
u64 mac1, mac2;
|
|
u8 mac_addr1[6], mac_addr2[6];
|
|
int num_macs;
|
|
|
|
/* try reading mac address from efuse */
|
|
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
|
|
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
|
|
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
mac_addr[2] = mac_hi & 0xFF;
|
|
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
|
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
|
mac_addr[5] = mac_lo & 0xFF;
|
|
|
|
if (!getenv("ethaddr")) {
|
|
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
|
|
|
if (is_valid_ethaddr(mac_addr))
|
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
|
}
|
|
|
|
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
|
|
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
|
|
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
mac_addr[2] = mac_hi & 0xFF;
|
|
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
|
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
|
mac_addr[5] = mac_lo & 0xFF;
|
|
|
|
if (!getenv("eth1addr")) {
|
|
if (is_valid_ethaddr(mac_addr))
|
|
eth_setenv_enetaddr("eth1addr", mac_addr);
|
|
}
|
|
|
|
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
|
|
ctrl_val |= 0x22;
|
|
writel(ctrl_val, (*ctrl)->control_core_control_io1);
|
|
|
|
/* The phy address for the AM572x IDK are different than x15 */
|
|
if (board_is_am572x_idk()) {
|
|
cpsw_data.slave_data[0].phy_addr = 0;
|
|
cpsw_data.slave_data[1].phy_addr = 1;
|
|
}
|
|
|
|
ret = cpsw_register(&cpsw_data);
|
|
if (ret < 0)
|
|
printf("Error %d registering CPSW switch\n", ret);
|
|
|
|
/*
|
|
* Export any Ethernet MAC addresses from EEPROM.
|
|
* On AM57xx the 2 MAC addresses define the address range
|
|
*/
|
|
board_ti_get_eth_mac_addr(0, mac_addr1);
|
|
board_ti_get_eth_mac_addr(1, mac_addr2);
|
|
|
|
if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
|
|
mac1 = mac_to_u64(mac_addr1);
|
|
mac2 = mac_to_u64(mac_addr2);
|
|
|
|
/* must contain an address range */
|
|
num_macs = mac2 - mac1 + 1;
|
|
/* <= 50 to protect against user programming error */
|
|
if (num_macs > 0 && num_macs <= 50) {
|
|
for (i = 0; i < num_macs; i++) {
|
|
u64_to_mac(mac1 + i, mac_addr);
|
|
if (is_valid_ethaddr(mac_addr)) {
|
|
eth_setenv_enetaddr_by_index("eth",
|
|
i + 2,
|
|
mac_addr);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
|
/* VTT regulator enable */
|
|
static inline void vtt_regulator_enable(void)
|
|
{
|
|
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
|
|
return;
|
|
|
|
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
|
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
vtt_regulator_enable();
|
|
return 0;
|
|
}
|
|
#endif
|