mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-09 11:43:48 +09:00
cecf2db23b
When compiled SPL for Thumb secondary cores failed to boot at the kernel boot up. Only one core came up out of 4. This was happening because the code relocated to the address 0x02073000 by the primary core was an ARM asm code which was executed by the secondary cores as if it was a thumb code. This patch fixes the issue of secondary cores considering relocated code as Thumb instructions and not ARM instructions by jumping to the relocated with the help of "bx" ARM instruction. "bx" instruction changes the 5th bit of CPSR which allows execution unit to consider the following instructions as ARM instructions. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> |
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| .. | ||
| clock_init_exynos4.c | ||
| clock_init_exynos5.c | ||
| clock_init.h | ||
| clock.c | ||
| common_setup.h | ||
| config.mk | ||
| dmc_common.c | ||
| dmc_init_ddr3.c | ||
| dmc_init_exynos4.c | ||
| exynos4_setup.h | ||
| exynos5_setup.h | ||
| Kconfig | ||
| lowlevel_init.c | ||
| Makefile | ||
| pinmux.c | ||
| power.c | ||
| sec_boot.S | ||
| soc.c | ||
| spl_boot.c | ||
| system.c | ||
| tzpc.c | ||