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![Jagan Teki](/assets/img/avatar_default.png)
Remove spi_init definition which never used on respective code since from many years. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
583 lines
14 KiB
C
583 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Driver for SPI controller on DaVinci. Based on atmel_spi.c
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* by Atmel Corporation
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*
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* Copyright (C) 2007 Atmel Corporation
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <dm.h>
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#include <dm/platform_data/spi_davinci.h>
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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#define SPIGCR0_SPIRST_MASK 0x0
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/* SPIGCR0 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_EN0FUN_MASK BIT(0)
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/* SPIFMT0 */
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#define SPIFMT_SHIFTDIR_SHIFT 20
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#define SPIFMT_POLARITY_SHIFT 17
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#define SPIFMT_PHASE_SHIFT 16
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSNR_SHIFT 16
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/* SPIDELAY */
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#define SPI_C2TDELAY_SHIFT 24
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#define SPI_T2CDELAY_SHIFT 16
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/* SPIBUF */
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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#define SPIBUF_TXFULL_MASK BIT(29)
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#ifndef CONFIG_DM_SPI
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#define SPI0_BUS 0
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#define SPI0_BASE CONFIG_SYS_SPI_BASE
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/*
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* Define default SPI0_NUM_CS as 1 for existing platforms that uses this
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* driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
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* if more than one CS is supported and by defining CONFIG_SYS_SPI0.
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*/
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#ifndef CONFIG_SYS_SPI0
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#define SPI0_NUM_CS 1
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#else
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#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
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#endif
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/*
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* define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
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* CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI1
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#define SPI1_BUS 1
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#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
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#define SPI1_BASE CONFIG_SYS_SPI1_BASE
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#endif
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/*
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* define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
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* CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI2
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#define SPI2_BUS 2
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#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* davinci spi register set */
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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/* davinci spi slave */
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struct davinci_spi_slave {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#endif
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struct davinci_spi_regs *regs;
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unsigned int freq; /* current SPI bus frequency */
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unsigned int mode; /* current SPI mode used */
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u8 num_cs; /* total no. of CS available */
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u8 cur_cs; /* CS of current slave */
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bool half_duplex; /* true, if master is half-duplex only */
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};
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/*
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* This functions needs to act like a macro to avoid pipeline reloads in the
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* loops below. Use always_inline. This gains us about 160KiB/s and the bloat
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* appears to be zero bytes (da830).
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*/
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__attribute__((always_inline))
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static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
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{
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u32 buf_reg_val;
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/* send out data */
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writel(data, &ds->regs->dat1);
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/* wait for the data to clock in/out */
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while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
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;
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return buf_reg_val;
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}
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static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
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u8 *rxp, unsigned long flags)
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{
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unsigned int data1_reg_val;
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/* enable CS hold, CS[n] and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* preload the TX buffer to avoid clock starvation */
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writel(data1_reg_val, &ds->regs->dat1);
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/* keep reading 1 byte until only 1 byte left */
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while ((len--) > 1)
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*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* read the last byte */
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*rxp = davinci_spi_xfer_data(ds, data1_reg_val);
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return 0;
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}
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static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
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const u8 *txp, unsigned long flags)
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{
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* preload the TX buffer to avoid clock starvation */
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if (len > 2) {
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writel(data1_reg_val | *txp++, &ds->regs->dat1);
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len--;
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}
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/* keep writing 1 byte until only 1 byte left */
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while ((len--) > 1)
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davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* write the last byte */
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davinci_spi_xfer_data(ds, data1_reg_val | *txp);
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return 0;
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}
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static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
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int len, u8 *rxp, const u8 *txp,
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unsigned long flags)
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{
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* keep reading and writing 1 byte until only 1 byte left */
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while ((len--) > 1)
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*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* read and write the last byte */
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*rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
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return 0;
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}
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static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
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{
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unsigned int mode = 0, scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* MSB shifted out first
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*/
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if (ds->mode & SPI_CPOL)
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mode |= SPI_CPOL;
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if (!(ds->mode & SPI_CPHA))
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mode |= SPI_CPHA;
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
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{
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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return 0;
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}
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static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
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unsigned int bitlen, const void *dout, void *din,
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unsigned long flags)
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{
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unsigned int len;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* It's not clear how non-8-bit-aligned transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface - here we terminate on receiving such a
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* transfer request.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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if (!dout)
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return davinci_spi_read(ds, len, din, flags);
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if (!din)
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return davinci_spi_write(ds, len, dout, flags);
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if (!ds->half_duplex)
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return davinci_spi_read_write(ds, len, din, dout, flags);
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printf("SPI full duplex not supported\n");
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flags |= SPI_XFER_END;
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out:
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if (flags & SPI_XFER_END) {
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u8 dummy = 0;
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davinci_spi_write(ds, 1, &dummy, flags);
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}
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return 0;
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}
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#ifndef CONFIG_DM_SPI
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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int ret = 0;
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switch (bus) {
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case SPI0_BUS:
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if (cs < SPI0_NUM_CS)
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ret = 1;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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if (cs < SPI1_NUM_CS)
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ret = 1;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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if (cs < SPI2_NUM_CS)
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ret = 1;
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break;
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#endif
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default:
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/* Invalid bus number. Do nothing */
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break;
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}
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return ret;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct davinci_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
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if (!ds)
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return NULL;
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switch (bus) {
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case SPI0_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
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break;
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#endif
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default: /* Invalid bus number */
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return NULL;
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}
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ds->freq = max_hz;
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ds->mode = mode;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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free(ds);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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ds->cur_cs = slave->cs;
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return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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#ifdef CONFIG_SPI_HALF_DUPLEX
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ds->half_duplex = true;
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#else
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ds->half_duplex = false;
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#endif
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return __davinci_spi_claim_bus(ds, ds->slave.cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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__davinci_spi_release_bus(ds);
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}
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#else
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static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
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{
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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debug("%s speed %u\n", __func__, max_hz);
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if (max_hz > CONFIG_SYS_SPI_CLK / 2)
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return -EINVAL;
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ds->freq = max_hz;
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return 0;
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}
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static int davinci_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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debug("%s mode %u\n", __func__, mode);
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ds->mode = mode;
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return 0;
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}
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static int davinci_spi_claim_bus(struct udevice *dev)
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{
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struct dm_spi_slave_platdata *slave_plat =
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dev_get_parent_platdata(dev);
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struct udevice *bus = dev->parent;
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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if (slave_plat->cs >= ds->num_cs) {
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printf("Invalid SPI chipselect\n");
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return -EINVAL;
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}
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ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
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return __davinci_spi_claim_bus(ds, slave_plat->cs);
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}
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static int davinci_spi_release_bus(struct udevice *dev)
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{
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struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
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return __davinci_spi_release_bus(ds);
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}
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static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din,
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unsigned long flags)
|
|
{
|
|
struct dm_spi_slave_platdata *slave =
|
|
dev_get_parent_platdata(dev);
|
|
struct udevice *bus = dev->parent;
|
|
struct davinci_spi_slave *ds = dev_get_priv(bus);
|
|
|
|
if (slave->cs >= ds->num_cs) {
|
|
printf("Invalid SPI chipselect\n");
|
|
return -EINVAL;
|
|
}
|
|
ds->cur_cs = slave->cs;
|
|
|
|
return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
|
|
}
|
|
|
|
static const struct dm_spi_ops davinci_spi_ops = {
|
|
.claim_bus = davinci_spi_claim_bus,
|
|
.release_bus = davinci_spi_release_bus,
|
|
.xfer = davinci_spi_xfer,
|
|
.set_speed = davinci_spi_set_speed,
|
|
.set_mode = davinci_spi_set_mode,
|
|
};
|
|
|
|
static int davinci_spi_probe(struct udevice *bus)
|
|
{
|
|
struct davinci_spi_slave *ds = dev_get_priv(bus);
|
|
struct davinci_spi_platdata *plat = bus->platdata;
|
|
ds->regs = plat->regs;
|
|
ds->num_cs = plat->num_cs;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
static int davinci_ofdata_to_platadata(struct udevice *bus)
|
|
{
|
|
struct davinci_spi_platdata *plat = bus->platdata;
|
|
fdt_addr_t addr;
|
|
|
|
addr = devfdt_get_addr(bus);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
plat->regs = (struct davinci_spi_regs *)addr;
|
|
plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id davinci_spi_ids[] = {
|
|
{ .compatible = "ti,keystone-spi" },
|
|
{ .compatible = "ti,dm6441-spi" },
|
|
{ .compatible = "ti,da830-spi" },
|
|
{ }
|
|
};
|
|
#endif
|
|
|
|
U_BOOT_DRIVER(davinci_spi) = {
|
|
.name = "davinci_spi",
|
|
.id = UCLASS_SPI,
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
.of_match = davinci_spi_ids,
|
|
.ofdata_to_platdata = davinci_ofdata_to_platadata,
|
|
.platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
|
|
#endif
|
|
.probe = davinci_spi_probe,
|
|
.ops = &davinci_spi_ops,
|
|
.priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
|
|
};
|
|
#endif
|