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![Marek Vasut](/assets/img/avatar_default.png)
Read ICSR only once to avoid missing interrupts. This happens on R8A7791 Porter during reset, when reading the PMIC register 0x13, which may fail sometimes because of the missed DTE interrupt. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Heiko Schocher <hs@denx.de>
273 lines
5.8 KiB
C
273 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar IIC driver
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on
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* Copyright (C) 2011, 2013 Renesas Solutions Corp.
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* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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struct rcar_iic_priv {
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void __iomem *base;
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struct clk clk;
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u8 iccl;
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u8 icch;
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};
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#define RCAR_IIC_ICDR 0x00
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#define RCAR_IIC_ICCR 0x04
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#define RCAR_IIC_ICSR 0x08
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#define RCAR_IIC_ICIC 0x0c
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#define RCAR_IIC_ICCL 0x10
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#define RCAR_IIC_ICCH 0x14
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/* ICCR */
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#define RCAR_IIC_ICCR_ICE BIT(7)
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#define RCAR_IIC_ICCR_RACK BIT(6)
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#define RCAR_IIC_ICCR_RTS BIT(4)
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#define RCAR_IIC_ICCR_BUSY BIT(2)
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#define RCAR_IIC_ICCR_SCP BIT(0)
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/* ICSR / ICIC */
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#define RCAR_IC_BUSY BIT(4)
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#define RCAR_IC_TACK BIT(2)
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#define RCAR_IC_DTE BIT(0)
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#define IRQ_WAIT 1000
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static void sh_irq_dte(struct udevice *dev)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int i;
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for (i = 0; i < IRQ_WAIT; i++) {
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if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
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break;
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udelay(10);
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}
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}
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static int sh_irq_dte_with_tack(struct udevice *dev)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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u8 icsr;
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int i;
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for (i = 0; i < IRQ_WAIT; i++) {
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icsr = readb(priv->base + RCAR_IIC_ICSR);
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if (RCAR_IC_DTE & icsr)
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break;
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if (RCAR_IC_TACK & icsr)
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return -ETIMEDOUT;
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udelay(10);
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}
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return 0;
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}
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static void sh_irq_busy(struct udevice *dev)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int i;
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for (i = 0; i < IRQ_WAIT; i++) {
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if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR)))
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break;
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udelay(10);
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}
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}
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static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
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setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
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writeb(priv->iccl, priv->base + RCAR_IIC_ICCL);
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writeb(priv->icch, priv->base + RCAR_IIC_ICCH);
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writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC);
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writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY,
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priv->base + RCAR_IIC_ICCR);
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sh_irq_dte(dev);
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clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK);
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writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR);
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return sh_irq_dte_with_tack(dev);
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}
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static void rcar_iic_finish(struct udevice *dev)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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writeb(0, priv->base + RCAR_IIC_ICSR);
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clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE);
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}
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static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int i, ret = -EREMOTEIO;
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if (rcar_iic_set_addr(dev, msg->addr, 1) != 0)
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goto err;
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udelay(10);
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writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
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priv->base + RCAR_IIC_ICCR);
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for (i = 0; i < msg->len; i++) {
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if (sh_irq_dte_with_tack(dev) != 0)
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goto err;
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msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff;
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if (msg->len - 1 == i) {
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writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK,
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priv->base + RCAR_IIC_ICCR);
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}
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}
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sh_irq_busy(dev);
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ret = 0;
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err:
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rcar_iic_finish(dev);
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return ret;
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}
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static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int i, ret = -EREMOTEIO;
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if (rcar_iic_set_addr(dev, msg->addr, 0) != 0)
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goto err;
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udelay(10);
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for (i = 0; i < msg->len; i++) {
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writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto err;
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}
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if (msg->flags & I2C_M_STOP) {
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writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS,
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priv->base + RCAR_IIC_ICCR);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto err;
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}
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sh_irq_busy(dev);
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ret = 0;
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err:
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rcar_iic_finish(dev);
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return ret;
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}
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static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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{
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int ret;
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for (; nmsgs > 0; nmsgs--, msg++) {
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if (msg->flags & I2C_M_RD)
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ret = rcar_iic_read_common(dev, msg);
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else
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ret = rcar_iic_write_common(dev, msg);
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if (ret)
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return -EREMOTEIO;
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}
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return ret;
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}
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static int rcar_iic_set_speed(struct udevice *dev, uint speed)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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const unsigned int ratio_high = 4;
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const unsigned int ratio_low = 5;
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int clkrate, denom;
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clkrate = clk_get_rate(&priv->clk);
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if (clkrate < 0)
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return clkrate;
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/*
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* Calculate the value for ICCL and ICCH. From the data sheet:
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* iccl = (p-clock / transfer-rate) * (L / (L + H))
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* icch = (p clock / transfer rate) * (H / (L + H))
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* where L and H are the SCL low and high ratio.
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*/
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denom = speed * (ratio_high + ratio_low);
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priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom);
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priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom);
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return 0;
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}
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static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int ret;
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rcar_iic_set_addr(dev, addr, 1);
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writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
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priv->base + RCAR_IIC_ICCR);
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ret = sh_irq_dte_with_tack(dev);
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rcar_iic_finish(dev);
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return ret;
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}
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static int rcar_iic_probe(struct udevice *dev)
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{
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struct rcar_iic_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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rcar_iic_finish(dev);
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return rcar_iic_set_speed(dev, 100000);
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}
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static const struct dm_i2c_ops rcar_iic_ops = {
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.xfer = rcar_iic_xfer,
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.probe_chip = rcar_iic_probe_chip,
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.set_bus_speed = rcar_iic_set_speed,
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};
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static const struct udevice_id rcar_iic_ids[] = {
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{ .compatible = "renesas,rmobile-iic" },
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{ }
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};
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U_BOOT_DRIVER(iic_rcar) = {
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.name = "iic_rcar",
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.id = UCLASS_I2C,
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.of_match = rcar_iic_ids,
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.probe = rcar_iic_probe,
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.priv_auto_alloc_size = sizeof(struct rcar_iic_priv),
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.ops = &rcar_iic_ops,
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};
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