mirror of
https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
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*
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* Copyright 2010 eXMeritus, A Boeing Company
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*/
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#include <common.h>
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#include <dm.h>
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#include <mapmem.h>
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#include <asm/gpio.h>
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struct ccsr_gpio {
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u32 gpdir;
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u32 gpodr;
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u32 gpdat;
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u32 gpier;
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u32 gpimr;
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u32 gpicr;
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};
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struct mpc8xxx_gpio_data {
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/* The bank's register base in memory */
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struct ccsr_gpio __iomem *base;
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/* The address of the registers; used to identify the bank */
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ulong addr;
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/* The GPIO count of the bank */
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uint gpio_count;
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/* The GPDAT register cannot be used to determine the value of output
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* pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
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* for output pins
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*/
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u32 dat_shadow;
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ulong type;
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};
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enum {
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MPC8XXX_GPIO_TYPE,
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MPC5121_GPIO_TYPE,
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};
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inline u32 gpio_mask(uint gpio)
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{
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return (1U << (31 - (gpio)));
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}
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static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpdat) & mask;
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}
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static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpdir) & mask;
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}
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static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
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{
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clrbits_be32(&base->gpdat, gpios);
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/* GPDIR register 0 -> input */
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clrbits_be32(&base->gpdir, gpios);
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}
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static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
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{
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clrbits_be32(&base->gpdat, gpios);
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/* GPDIR register 1 -> output */
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setbits_be32(&base->gpdir, gpios);
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}
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static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
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{
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setbits_be32(&base->gpdat, gpios);
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/* GPDIR register 1 -> output */
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setbits_be32(&base->gpdir, gpios);
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}
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static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpodr) & mask;
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}
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static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
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gpios)
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{
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/* GPODR register 1 -> open drain on */
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setbits_be32(&base->gpodr, gpios);
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}
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static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
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u32 gpios)
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{
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/* GPODR register 0 -> open drain off (actively driven) */
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clrbits_be32(&base->gpodr, gpios);
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}
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static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
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return 0;
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}
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static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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if (value) {
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data->dat_shadow |= gpio_mask(gpio);
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mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
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} else {
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data->dat_shadow &= ~gpio_mask(gpio);
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mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
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}
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return 0;
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}
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static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
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int value)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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/* GPIO 28..31 are input only on MPC5121 */
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if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
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return -EINVAL;
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return mpc8xxx_gpio_set_value(dev, gpio, value);
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}
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static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
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/* Output -> use shadowed value */
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return !!(data->dat_shadow & gpio_mask(gpio));
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}
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/* Input -> read value from GPDAT register */
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return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
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}
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static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
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}
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static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
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int value)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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if (value)
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mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
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else
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mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
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return 0;
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}
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static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
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{
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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int dir;
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dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
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return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
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fdt_addr_t addr;
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u32 reg[2];
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dev_read_u32_array(dev, "reg", reg, 2);
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addr = dev_translate_address(dev, reg);
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plat->addr = addr;
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plat->size = reg[1];
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plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
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return 0;
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}
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#endif
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static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
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{
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struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
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struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
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unsigned long size = plat->size;
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ulong driver_data = dev_get_driver_data(dev);
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if (size == 0)
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size = 0x100;
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priv->addr = plat->addr;
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priv->base = map_sysmem(plat->addr, size);
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if (!priv->base)
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return -ENOMEM;
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priv->gpio_count = plat->ngpios;
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priv->dat_shadow = 0;
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priv->type = driver_data;
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return 0;
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}
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static int mpc8xxx_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
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char name[32], *str;
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mpc8xxx_gpio_platdata_to_priv(dev);
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snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = data->gpio_count;
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return 0;
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}
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static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
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.direction_input = mpc8xxx_gpio_direction_input,
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.direction_output = mpc8xxx_gpio_direction_output,
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.get_value = mpc8xxx_gpio_get_value,
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.set_value = mpc8xxx_gpio_set_value,
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.get_open_drain = mpc8xxx_gpio_get_open_drain,
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.set_open_drain = mpc8xxx_gpio_set_open_drain,
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.get_function = mpc8xxx_gpio_get_function,
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};
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static const struct udevice_id mpc8xxx_gpio_ids[] = {
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{ .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
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{ .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
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{ .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
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{ .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
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{ .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
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{ .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
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{ .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(gpio_mpc8xxx) = {
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.name = "gpio_mpc8xxx",
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.id = UCLASS_GPIO,
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.ops = &gpio_mpc8xxx_ops,
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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.ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
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.of_match = mpc8xxx_gpio_ids,
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#endif
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.probe = mpc8xxx_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
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};
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