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![Patrice Chotard](/assets/img/avatar_default.png)
"st,stm32-qspi" is no more used, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
541 lines
12 KiB
C
541 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016
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*
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* Michael Kurz, <michi.kurz@gmail.com>
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*
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* STM32 QSPI driver
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*/
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#include <common.h>
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#include <clk.h>
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#include <reset.h>
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#include <spi-mem.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/sizes.h>
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struct stm32_qspi_regs {
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u32 cr; /* 0x00 */
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u32 dcr; /* 0x04 */
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u32 sr; /* 0x08 */
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u32 fcr; /* 0x0C */
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u32 dlr; /* 0x10 */
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u32 ccr; /* 0x14 */
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u32 ar; /* 0x18 */
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u32 abr; /* 0x1C */
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u32 dr; /* 0x20 */
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u32 psmkr; /* 0x24 */
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u32 psmar; /* 0x28 */
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u32 pir; /* 0x2C */
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u32 lptr; /* 0x30 */
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};
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/*
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* QUADSPI control register
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*/
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#define STM32_QSPI_CR_EN BIT(0)
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#define STM32_QSPI_CR_ABORT BIT(1)
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#define STM32_QSPI_CR_DMAEN BIT(2)
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#define STM32_QSPI_CR_TCEN BIT(3)
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#define STM32_QSPI_CR_SSHIFT BIT(4)
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#define STM32_QSPI_CR_DFM BIT(6)
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#define STM32_QSPI_CR_FSEL BIT(7)
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#define STM32_QSPI_CR_FTHRES_SHIFT 8
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#define STM32_QSPI_CR_TEIE BIT(16)
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#define STM32_QSPI_CR_TCIE BIT(17)
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#define STM32_QSPI_CR_FTIE BIT(18)
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#define STM32_QSPI_CR_SMIE BIT(19)
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#define STM32_QSPI_CR_TOIE BIT(20)
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#define STM32_QSPI_CR_APMS BIT(22)
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#define STM32_QSPI_CR_PMM BIT(23)
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#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
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#define STM32_QSPI_CR_PRESCALER_SHIFT 24
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/*
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* QUADSPI device configuration register
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*/
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#define STM32_QSPI_DCR_CKMODE BIT(0)
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#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
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#define STM32_QSPI_DCR_CSHT_SHIFT 8
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#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
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#define STM32_QSPI_DCR_FSIZE_SHIFT 16
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/*
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* QUADSPI status register
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*/
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#define STM32_QSPI_SR_TEF BIT(0)
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#define STM32_QSPI_SR_TCF BIT(1)
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#define STM32_QSPI_SR_FTF BIT(2)
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#define STM32_QSPI_SR_SMF BIT(3)
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#define STM32_QSPI_SR_TOF BIT(4)
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#define STM32_QSPI_SR_BUSY BIT(5)
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/*
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* QUADSPI flag clear register
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*/
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#define STM32_QSPI_FCR_CTEF BIT(0)
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#define STM32_QSPI_FCR_CTCF BIT(1)
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#define STM32_QSPI_FCR_CSMF BIT(3)
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#define STM32_QSPI_FCR_CTOF BIT(4)
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/*
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* QUADSPI communication configuration register
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*/
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#define STM32_QSPI_CCR_DDRM BIT(31)
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#define STM32_QSPI_CCR_DHHC BIT(30)
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#define STM32_QSPI_CCR_SIOO BIT(28)
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#define STM32_QSPI_CCR_FMODE_SHIFT 26
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#define STM32_QSPI_CCR_DMODE_SHIFT 24
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#define STM32_QSPI_CCR_DCYC_SHIFT 18
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#define STM32_QSPI_CCR_ABSIZE_SHIFT 16
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#define STM32_QSPI_CCR_ABMODE_SHIFT 14
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#define STM32_QSPI_CCR_ADSIZE_SHIFT 12
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#define STM32_QSPI_CCR_ADMODE_SHIFT 10
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#define STM32_QSPI_CCR_IMODE_SHIFT 8
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#define STM32_QSPI_CCR_IND_WRITE 0
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#define STM32_QSPI_CCR_IND_READ 1
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#define STM32_QSPI_CCR_MEM_MAP 3
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#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
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#define STM32_QSPI_MAX_CHIP 2
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#define STM32_QSPI_FIFO_TIMEOUT_US 30000
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#define STM32_QSPI_CMD_TIMEOUT_US 1000000
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#define STM32_BUSY_TIMEOUT_US 100000
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#define STM32_ABT_TIMEOUT_US 100000
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struct stm32_qspi_flash {
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u32 cr;
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u32 dcr;
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bool initialized;
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};
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struct stm32_qspi_priv {
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struct stm32_qspi_regs *regs;
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struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
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void __iomem *mm_base;
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resource_size_t mm_size;
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ulong clock_rate;
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int cs_used;
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};
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static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
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{
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u32 sr;
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int ret;
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ret = readl_poll_timeout(&priv->regs->sr, sr,
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!(sr & STM32_QSPI_SR_BUSY),
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STM32_BUSY_TIMEOUT_US);
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if (ret)
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pr_err("busy timeout (stat:%#x)\n", sr);
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return ret;
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}
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static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
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const struct spi_mem_op *op)
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{
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u32 sr;
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int ret;
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if (!op->data.nbytes)
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return _stm32_qspi_wait_for_not_busy(priv);
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ret = readl_poll_timeout(&priv->regs->sr, sr,
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sr & STM32_QSPI_SR_TCF,
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STM32_QSPI_CMD_TIMEOUT_US);
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if (ret) {
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pr_err("cmd timeout (stat:%#x)\n", sr);
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} else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
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pr_err("transfer error (stat:%#x)\n", sr);
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ret = -EIO;
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}
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/* clear flags */
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writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
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return ret;
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}
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static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
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{
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*val = readb(addr);
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}
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static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
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{
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writeb(*val, addr);
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}
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static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
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const struct spi_mem_op *op)
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{
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void (*fifo)(u8 *val, void __iomem *addr);
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u32 len = op->data.nbytes, sr;
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u8 *buf;
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int ret;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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fifo = _stm32_qspi_read_fifo;
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buf = op->data.buf.in;
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} else {
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fifo = _stm32_qspi_write_fifo;
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buf = (u8 *)op->data.buf.out;
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}
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while (len--) {
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ret = readl_poll_timeout(&priv->regs->sr, sr,
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sr & STM32_QSPI_SR_FTF,
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STM32_QSPI_FIFO_TIMEOUT_US);
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if (ret) {
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pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
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return ret;
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}
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fifo(buf++, &priv->regs->dr);
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}
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return 0;
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}
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static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
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const struct spi_mem_op *op)
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{
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memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
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op->data.nbytes);
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return 0;
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}
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static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
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const struct spi_mem_op *op,
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u8 mode)
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{
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if (!op->data.nbytes)
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return 0;
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if (mode == STM32_QSPI_CCR_MEM_MAP)
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return stm32_qspi_mm(priv, op);
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return _stm32_qspi_poll(priv, op);
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}
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static int _stm32_qspi_get_mode(u8 buswidth)
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{
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if (buswidth == 4)
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return 3;
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return buswidth;
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}
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static int stm32_qspi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
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u32 cr, ccr, addr_max;
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u8 mode = STM32_QSPI_CCR_IND_WRITE;
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int timeout, ret;
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debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
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__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->dummy.buswidth, op->data.buswidth,
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op->addr.val, op->data.nbytes);
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ret = _stm32_qspi_wait_for_not_busy(priv);
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if (ret)
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return ret;
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addr_max = op->addr.val + op->data.nbytes + 1;
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if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
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if (addr_max < priv->mm_size && op->addr.buswidth)
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mode = STM32_QSPI_CCR_MEM_MAP;
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else
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mode = STM32_QSPI_CCR_IND_READ;
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}
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if (op->data.nbytes)
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writel(op->data.nbytes - 1, &priv->regs->dlr);
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ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
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ccr |= op->cmd.opcode;
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ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
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<< STM32_QSPI_CCR_IMODE_SHIFT);
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if (op->addr.nbytes) {
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ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
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ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
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<< STM32_QSPI_CCR_ADMODE_SHIFT);
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}
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if (op->dummy.buswidth && op->dummy.nbytes)
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ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
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<< STM32_QSPI_CCR_DCYC_SHIFT);
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if (op->data.nbytes)
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ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
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<< STM32_QSPI_CCR_DMODE_SHIFT);
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writel(ccr, &priv->regs->ccr);
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if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
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writel(op->addr.val, &priv->regs->ar);
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ret = _stm32_qspi_tx(priv, op, mode);
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/*
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* Abort in:
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* -error case
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* -read memory map: prefetching must be stopped if we read the last
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* byte of device (device size - fifo size). like device size is not
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* knows, the prefetching is always stop.
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*/
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if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
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goto abort;
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/* Wait end of tx in indirect mode */
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ret = _stm32_qspi_wait_cmd(priv, op);
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if (ret)
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goto abort;
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return 0;
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abort:
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setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
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/* Wait clear of abort bit by hw */
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timeout = readl_poll_timeout(&priv->regs->cr, cr,
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!(cr & STM32_QSPI_CR_ABORT),
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STM32_ABT_TIMEOUT_US);
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writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
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if (ret || timeout)
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pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
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return ret;
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}
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static int stm32_qspi_probe(struct udevice *bus)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(bus);
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struct resource res;
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struct clk clk;
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struct reset_ctl reset_ctl;
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int ret;
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ret = dev_read_resource_byname(bus, "qspi", &res);
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if (ret) {
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dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
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return ret;
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}
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priv->regs = (struct stm32_qspi_regs *)res.start;
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ret = dev_read_resource_byname(bus, "qspi_mm", &res);
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if (ret) {
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dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
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return ret;
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}
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priv->mm_base = (void __iomem *)res.start;
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priv->mm_size = resource_size(&res);
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if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
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return -EINVAL;
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debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
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__func__, priv->regs, priv->mm_base, priv->mm_size);
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ret = clk_get_by_index(bus, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(bus, "failed to enable clock\n");
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return ret;
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}
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priv->clock_rate = clk_get_rate(&clk);
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if (!priv->clock_rate) {
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clk_disable(&clk);
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return -EINVAL;
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}
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ret = reset_get_by_index(bus, 0, &reset_ctl);
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if (ret) {
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if (ret != -ENOENT) {
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dev_err(bus, "failed to get reset\n");
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clk_disable(&clk);
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return ret;
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}
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} else {
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/* Reset QSPI controller */
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reset_assert(&reset_ctl);
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udelay(2);
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reset_deassert(&reset_ctl);
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}
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priv->cs_used = -1;
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setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
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/* Set dcr fsize to max address */
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setbits_le32(&priv->regs->dcr,
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STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
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return 0;
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}
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static int stm32_qspi_claim_bus(struct udevice *dev)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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int slave_cs = slave_plat->cs;
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if (slave_cs >= STM32_QSPI_MAX_CHIP)
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return -ENODEV;
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if (priv->cs_used != slave_cs) {
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struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
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priv->cs_used = slave_cs;
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if (flash->initialized) {
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/* Set the configuration: speed + cs */
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writel(flash->cr, &priv->regs->cr);
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writel(flash->dcr, &priv->regs->dcr);
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} else {
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/* Set chip select */
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clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
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priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
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/* Save the configuration: speed + cs */
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flash->cr = readl(&priv->regs->cr);
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flash->dcr = readl(&priv->regs->dcr);
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flash->initialized = true;
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}
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}
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setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
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return 0;
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}
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static int stm32_qspi_release_bus(struct udevice *dev)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
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clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
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return 0;
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}
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static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(bus);
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u32 qspi_clk = priv->clock_rate;
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u32 prescaler = 255;
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u32 csht;
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int ret;
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if (speed > 0) {
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prescaler = 0;
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if (qspi_clk) {
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prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
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if (prescaler > 255)
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prescaler = 255;
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}
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}
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csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
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csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
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ret = _stm32_qspi_wait_for_not_busy(priv);
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if (ret)
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return ret;
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clrsetbits_le32(&priv->regs->cr,
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STM32_QSPI_CR_PRESCALER_MASK <<
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STM32_QSPI_CR_PRESCALER_SHIFT,
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prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
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clrsetbits_le32(&priv->regs->dcr,
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STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
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csht << STM32_QSPI_DCR_CSHT_SHIFT);
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
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(qspi_clk / (prescaler + 1)));
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return 0;
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}
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static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
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{
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struct stm32_qspi_priv *priv = dev_get_priv(bus);
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int ret;
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ret = _stm32_qspi_wait_for_not_busy(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
|
|
setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
|
|
else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
|
|
clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
|
|
else
|
|
return -ENODEV;
|
|
|
|
if (mode & SPI_CS_HIGH)
|
|
return -ENODEV;
|
|
|
|
debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
|
|
|
|
if (mode & SPI_RX_QUAD)
|
|
debug("quad, tx: ");
|
|
else if (mode & SPI_RX_DUAL)
|
|
debug("dual, tx: ");
|
|
else
|
|
debug("single, tx: ");
|
|
|
|
if (mode & SPI_TX_QUAD)
|
|
debug("quad\n");
|
|
else if (mode & SPI_TX_DUAL)
|
|
debug("dual\n");
|
|
else
|
|
debug("single\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
|
|
.exec_op = stm32_qspi_exec_op,
|
|
};
|
|
|
|
static const struct dm_spi_ops stm32_qspi_ops = {
|
|
.claim_bus = stm32_qspi_claim_bus,
|
|
.release_bus = stm32_qspi_release_bus,
|
|
.set_speed = stm32_qspi_set_speed,
|
|
.set_mode = stm32_qspi_set_mode,
|
|
.mem_ops = &stm32_qspi_mem_ops,
|
|
};
|
|
|
|
static const struct udevice_id stm32_qspi_ids[] = {
|
|
{ .compatible = "st,stm32f469-qspi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32_qspi) = {
|
|
.name = "stm32_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = stm32_qspi_ids,
|
|
.ops = &stm32_qspi_ops,
|
|
.priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
|
|
.probe = stm32_qspi_probe,
|
|
};
|