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![Simon Goldschmidt](/assets/img/avatar_default.png)
Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to read flash (child node) parameters. Tested on socfpga_socrates (socfpga gen5). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
362 lines
9.4 KiB
C
362 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <reset.h>
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#include <spi.h>
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#include <linux/errno.h>
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#include "cadence_qspi.h"
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#define CQSPI_STIG_READ 0
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#define CQSPI_STIG_WRITE 1
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#define CQSPI_INDIRECT_READ 2
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#define CQSPI_INDIRECT_WRITE 3
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static int cadence_spi_write_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_platdata *plat = bus->platdata;
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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cadence_qspi_apb_config_baudrate_div(priv->regbase,
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CONFIG_CQSPI_REF_CLK, hz);
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/* Reconfigure delay timing if speed is changed. */
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cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
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plat->tshsl_ns, plat->tsd2d_ns,
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plat->tchsh_ns, plat->tslch_ns);
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return 0;
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}
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/* Calibration sequence to determine the read data capture delay register */
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static int spi_calibration(struct udevice *bus, uint hz)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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void *base = priv->regbase;
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u8 opcode_rdid = 0x9F;
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unsigned int idcode = 0, temp = 0;
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int err = 0, i, range_lo = -1, range_hi = -1;
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/* start with slowest clock (1 MHz) */
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cadence_spi_write_speed(bus, 1000000);
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/* configure the read data capture delay register to 0 */
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cadence_qspi_apb_readdata_capture(base, 1, 0);
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* read the ID which will be our golden value */
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err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
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3, (u8 *)&idcode);
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* use back the intended clock and find low range */
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cadence_spi_write_speed(bus, hz);
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for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(base);
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/* reconfigure the read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, i);
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/* Enable back QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* issue a RDID to get the ID value */
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err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
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3, (u8 *)&temp);
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* search for range lo */
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if (range_lo == -1 && temp == idcode) {
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range_lo = i;
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continue;
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}
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/* search for range hi */
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if (range_lo != -1 && temp != idcode) {
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range_hi = i - 1;
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break;
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}
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range_hi = i;
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}
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if (range_lo == -1) {
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puts("SF: Calibration failed (low range)\n");
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return err;
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}
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/* Disable QSPI for subsequent initialization */
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cadence_qspi_apb_controller_disable(base);
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/* configure the final value for read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
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debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
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(range_hi + range_lo) / 2, range_lo, range_hi);
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/* just to ensure we do once only when speed or chip select change */
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priv->qspi_calibrated_hz = hz;
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priv->qspi_calibrated_cs = spi_chip_select(bus);
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return 0;
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}
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static int cadence_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_platdata *plat = bus->platdata;
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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int err;
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if (hz > plat->max_hz)
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hz = plat->max_hz;
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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/*
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* Calibration required for different current SCLK speed, requested
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* SCLK speed or chip select
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*/
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if (priv->previous_hz != hz ||
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priv->qspi_calibrated_hz != hz ||
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priv->qspi_calibrated_cs != spi_chip_select(bus)) {
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err = spi_calibration(bus, hz);
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if (err)
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return err;
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/* prevent calibration run when same as previous request */
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priv->previous_hz = hz;
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}
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(priv->regbase);
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debug("%s: speed=%d\n", __func__, hz);
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return 0;
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}
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static int cadence_spi_probe(struct udevice *bus)
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{
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struct cadence_spi_platdata *plat = bus->platdata;
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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int ret;
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priv->regbase = plat->regbase;
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priv->ahbbase = plat->ahbbase;
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ret = reset_get_bulk(bus, &priv->resets);
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if (ret)
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dev_warn(bus, "Can't get reset: %d\n", ret);
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else
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reset_deassert_bulk(&priv->resets);
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if (!priv->qspi_is_init) {
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cadence_qspi_apb_controller_init(plat);
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priv->qspi_is_init = 1;
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}
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return 0;
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}
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static int cadence_spi_remove(struct udevice *dev)
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{
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struct cadence_spi_priv *priv = dev_get_priv(dev);
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return reset_release_bulk(&priv->resets);
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}
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static int cadence_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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/* Set SPI mode */
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cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(priv->regbase);
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return 0;
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}
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static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct cadence_spi_platdata *plat = bus->platdata;
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
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void *base = priv->regbase;
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u8 *cmd_buf = priv->cmd_buf;
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size_t data_bytes;
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int err = 0;
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u32 mode = CQSPI_STIG_WRITE;
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if (flags & SPI_XFER_BEGIN) {
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/* copy command to local buffer */
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priv->cmd_len = bitlen / 8;
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memcpy(cmd_buf, dout, priv->cmd_len);
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}
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if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
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/* if start and end bit are set, the data bytes is 0. */
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data_bytes = 0;
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} else {
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data_bytes = bitlen / 8;
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}
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debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
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/* Set Chip select */
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cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
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plat->is_decoded_cs);
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if ((flags & SPI_XFER_END) || (flags == 0)) {
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if (priv->cmd_len == 0) {
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printf("QSPI: Error, command is empty.\n");
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return -1;
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}
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if (din && data_bytes) {
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/* read */
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/* Use STIG if no address. */
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if (!CQSPI_IS_ADDR(priv->cmd_len))
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mode = CQSPI_STIG_READ;
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else
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mode = CQSPI_INDIRECT_READ;
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} else if (dout && !(flags & SPI_XFER_BEGIN)) {
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/* write */
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if (!CQSPI_IS_ADDR(priv->cmd_len))
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mode = CQSPI_STIG_WRITE;
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else
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mode = CQSPI_INDIRECT_WRITE;
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}
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switch (mode) {
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case CQSPI_STIG_READ:
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err = cadence_qspi_apb_command_read(
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base, priv->cmd_len, cmd_buf,
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data_bytes, din);
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break;
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case CQSPI_STIG_WRITE:
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err = cadence_qspi_apb_command_write(base,
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priv->cmd_len, cmd_buf,
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data_bytes, dout);
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break;
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case CQSPI_INDIRECT_READ:
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err = cadence_qspi_apb_indirect_read_setup(plat,
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priv->cmd_len, dm_plat->mode, cmd_buf);
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if (!err) {
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err = cadence_qspi_apb_indirect_read_execute
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(plat, data_bytes, din);
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}
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break;
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case CQSPI_INDIRECT_WRITE:
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err = cadence_qspi_apb_indirect_write_setup
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(plat, priv->cmd_len, dm_plat->mode, cmd_buf);
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if (!err) {
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err = cadence_qspi_apb_indirect_write_execute
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(plat, data_bytes, dout);
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}
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break;
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default:
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err = -1;
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break;
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}
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if (flags & SPI_XFER_END) {
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/* clear command buffer */
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memset(cmd_buf, 0, sizeof(priv->cmd_buf));
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priv->cmd_len = 0;
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}
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}
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return err;
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}
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static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct cadence_spi_platdata *plat = bus->platdata;
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ofnode subnode;
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plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
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plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
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plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
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plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
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plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
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plat->trigger_address = dev_read_u32_default(bus,
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"cdns,trigger-address",
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0);
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/* All other paramters are embedded in the child node */
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subnode = dev_read_first_subnode(bus);
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if (!ofnode_valid(subnode)) {
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printf("Error: subnode with SPI flash config missing!\n");
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return -ENODEV;
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}
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/* Use 500 KHz as a suitable default */
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plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
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500000);
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/* Read other parameters from DT */
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plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
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plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
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plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
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200);
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plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
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255);
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plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
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plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
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debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
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__func__, plat->regbase, plat->ahbbase, plat->max_hz,
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plat->page_size);
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return 0;
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}
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static const struct dm_spi_ops cadence_spi_ops = {
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.xfer = cadence_spi_xfer,
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.set_speed = cadence_spi_set_speed,
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.set_mode = cadence_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id cadence_spi_ids[] = {
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{ .compatible = "cdns,qspi-nor" },
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{ }
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};
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U_BOOT_DRIVER(cadence_spi) = {
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.name = "cadence_spi",
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.id = UCLASS_SPI,
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.of_match = cadence_spi_ids,
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.ops = &cadence_spi_ops,
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.ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
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.probe = cadence_spi_probe,
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.remove = cadence_spi_remove,
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.flags = DM_FLAG_OS_PREPARE,
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};
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