mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
5e7abce991
This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
415 lines
11 KiB
C
415 lines
11 KiB
C
/*
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*(C) Copyright 2005-2008 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/ppc440.h>
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#include <asm/io.h>
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#include <asm/4xx_pci.h>
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#include "../common/nm.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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#define SDR0_CP440 0x0180
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#define SYSTEM_RESET 0x30000000
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#define CHIP_RESET 0x20000000
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000)
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#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000)
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#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
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#define HCU_SW_INSTALL_REQUESTED 0x10
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/*
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* This function is run very early, out of flash, and before devices are
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* initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
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* of being in the init_sequence array.
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*
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* The SDRAM has been initialized already -- start.S:start called
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* init.S:init_sdram early on -- but it is not yet being used for
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* anything, not even stack. So be careful.
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*/
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int board_early_init_f(void)
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{
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#ifdef BOOTSTRAP_OPTION_A_ACTIVE
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/* Booting with Bootstrap Option A
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* First boot, with CPR0_ICFG_RLI_MASK == 0
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* no we setup varios boot strapping register,
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* then we do reset the PPC440 using a chip reset
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* Unfortunately, we cannot use this option, as Nto1 is not set
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* with Bootstrap Option A and cannot be changed later on by SW
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* There are no other possible boostrap options with a 8 bit ROM
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* See Errata (Version 1.04) CHIP_9
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*/
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u32 cpr0icfg;
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u32 dbcr;
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mfcpr(CPR0_ICFG, cpr0icfg);
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if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
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mtcpr(CPR0_MALD, 0x02000000);
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mtcpr(CPR0_OPBD, 0x02000000);
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mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
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mtcpr(CPR0_PLLC, 0x40000238);
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mtcpr(CPR0_PLLD, 0x01010414);
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mtcpr(CPR0_PRIMAD, 0x01000000);
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mtcpr(CPR0_PRIMBD, 0x01000000);
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mtcpr(CPR0_SPCID, 0x03000000);
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mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
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/*
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* Initiate system reset in debug control register DBCR
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*/
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dbcr = mfspr(SPRN_DBCR0);
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mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
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}
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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#endif
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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mtdcr(EBC0_CFGDATA, 0xb8400000);
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/*
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* Setup the GPIO pins
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*/
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out32(GPIO0_OR, 0x00000000);
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out32(GPIO0_TCR, 0x7C2FF1CF);
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out32(GPIO0_OSRL, 0x40055000);
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out32(GPIO0_OSRH, 0x00000000);
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out32(GPIO0_TSRL, 0x40055000);
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out32(GPIO0_TSRH, 0x00000400);
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out32(GPIO0_ISR1L, 0x40000000);
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out32(GPIO0_ISR1H, 0x00000000);
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out32(GPIO0_ISR2L, 0x00000000);
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out32(GPIO0_ISR2H, 0x00000000);
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out32(GPIO0_ISR3L, 0x00000000);
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out32(GPIO0_ISR3H, 0x00000000);
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out32(GPIO1_OR, 0x00000000);
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out32(GPIO1_TCR, 0xC6007FFF);
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out32(GPIO1_OSRL, 0x00140000);
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out32(GPIO1_OSRH, 0x00000000);
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out32(GPIO1_TSRL, 0x00000000);
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out32(GPIO1_TSRH, 0x00000000);
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out32(GPIO1_ISR1L, 0x05415555);
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out32(GPIO1_ISR1H, 0x40000000);
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out32(GPIO1_ISR2L, 0x00000000);
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out32(GPIO1_ISR2H, 0x00000000);
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out32(GPIO1_ISR3L, 0x00000000);
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out32(GPIO1_ISR3H, 0x00000000);
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
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mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
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/* setup BOOT FLASH */
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mtsdr(SDR0_CUST0, 0xC0082350);
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init(void)
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{
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return board_early_init_f();
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}
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#endif
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int sys_install_requested(void)
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{
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u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
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return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
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}
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int checkboard(void)
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{
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u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
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u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
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u16 generation = in_be16(boardVersReg) & 0xf0;
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u16 index = in_be16(boardVersReg) & 0x0f;
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u32 ecid0, ecid1, ecid2, ecid3;
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nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
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mfsdr(SDR0_ECID0, ecid0);
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mfsdr(SDR0_ECID1, ecid1);
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mfsdr(SDR0_ECID2, ecid2);
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mfsdr(SDR0_ECID3, ecid3);
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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return 0;
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}
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u32 hcu_led_get(void)
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{
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return in16(SYS_IO_ADDRESS) & 0x3f;
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}
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/*
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* hcu_led_set value to be placed into the LEDs (max 6 bit)
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*/
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void hcu_led_set(u32 value)
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{
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out16(SYS_IO_ADDRESS, value);
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}
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/*
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* get_serial_number
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*/
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u32 get_serial_number(void)
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{
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u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
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if (in_be32(serial) == 0xffffffff)
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return 0;
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return in_be32(serial);
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}
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/*
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* hcu_get_slot
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*/
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u32 hcu_get_slot(void)
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{
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u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
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return in_be16(slot) & 0x7f;
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}
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/*
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* misc_init_r.
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*/
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int misc_init_r(void)
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{
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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#ifdef CONFIG_ENV_ADDR_REDUND
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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#endif
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/*
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* USB stuff...
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*/
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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* when connecting the Device to the PHY
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*/
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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/* To enable the USB 2.0 Device function through the UTMI interface */
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usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
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usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
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sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
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sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB2D0CR, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*clear resets*/
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udelay(1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay(1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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common_misc_init_r();
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set_params_for_sw_install( sys_install_requested(), "hcu5" );
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/* We cannot easily enable trace before, as there are other
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* routines messing around with sdr0_pfc1. And I do not need it.
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*/
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if (mfspr(SPRN_DBCR0) & 0x80000000) {
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/* External debugger alive
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* enable trace facilty for Lauterbach
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* CCR0[DTB]=0 Enable broadcast of trace information
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* SDR0_PFC0[TRE] Trace signals are enabled instead of
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* GPIO49-63
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*/
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mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
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mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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int board_with_pci(void)
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{
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u32 reg;
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mfsdr(SDR0_PCI0, reg);
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return (reg & SDR0_PCI0_PAE_MASK);
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}
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/*
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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*/
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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if (!board_with_pci()) { return 0; }
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/*
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* Set priority for all PLB3 devices to 0.
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* Set PLB3 arbiter to fair mode.
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*/
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mfsdr(SDR0_AMP1, addr);
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mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(PLB3A0_ACR);
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mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
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/*
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* Set priority for all PLB4 devices to 0.
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*/
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mfsdr(SDR0_AMP0, addr);
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mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */
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mtdcr(PLB4A0_ACR, addr); /* Sequoia */
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/*
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* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
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* Workaround: Disable write pipelining to DDR SDRAM by setting
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* PLB4A0_ACR[WRP] = 0.
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*/
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mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
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/* Segment1 */
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mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
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return board_with_pci();
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}
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/*
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* Override weak default pci_master_init()
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*/
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void pci_master_init(struct pci_controller *hose)
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{
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if (!board_with_pci())
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return;
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__pci_master_init(hose);
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}
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#endif /* defined(CONFIG_PCI) */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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/*
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* Hardcoded flash setup:
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* Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
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*/
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = 1;
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info->chipwidth = 1;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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return 0;
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}
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