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https://github.com/brain-hackers/u-boot-brain
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21b02414f1
BD71837 and BD71847 is PMIC intended for powering single-core, dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847 is used for example on NXP imx8mm EVK. Add regulator driver for ROHM BD71837 and BD71847 PMICs. BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version containing 6 bucks and 6 LDOs. Voltages for DVS bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted when regulators are enabled. For other bucks and LDOs we may have over- or undershooting if voltage is adjusted when regulator is enabled. Thus this is prevented by default. BD718x7 has a quirk which may leave power output disabled after reset if enable/disable state was controlled by SW. Thus the SW control is only allowed for BD71837 bucks 3 and 4 by default. The impact of this limitation must be evaluated board-by board and restrictions may need to be modified. (Linux driver get's these limitations from DT and we may want to implement same on u-Boot driver). Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Simon Glass <sjg@chromium.org>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2018 ROHM Semiconductors */
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#ifndef BD718XX_H_
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#define BD718XX_H_
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#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
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enum {
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ROHM_CHIP_TYPE_BD71837 = 0,
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ROHM_CHIP_TYPE_BD71847,
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ROHM_CHIP_TYPE_BD70528,
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ROHM_CHIP_TYPE_AMOUNT
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};
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enum {
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BD718XX_REV = 0x00,
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BD718XX_SWRESET = 0x01,
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BD718XX_I2C_DEV = 0x02,
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BD718XX_PWRCTRL0 = 0x03,
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BD718XX_PWRCTRL1 = 0x04,
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BD718XX_BUCK1_CTRL = 0x05,
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BD718XX_BUCK2_CTRL = 0x06,
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BD71837_BUCK3_CTRL = 0x07,
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BD71837_BUCK4_CTRL = 0x08,
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BD718XX_1ST_NODVS_BUCK_CTRL = 0x09,
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BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a,
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BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b,
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BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c,
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BD718XX_BUCK1_VOLT_RUN = 0x0d,
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BD718XX_BUCK1_VOLT_IDLE = 0x0e,
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BD718XX_BUCK1_VOLT_SUSP = 0x0f,
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BD718XX_BUCK2_VOLT_RUN = 0x10,
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BD718XX_BUCK2_VOLT_IDLE = 0x11,
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BD71837_BUCK3_VOLT_RUN = 0x12,
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BD71837_BUCK4_VOLT_RUN = 0x13,
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BD718XX_1ST_NODVS_BUCK_VOLT = 0x14,
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BD718XX_2ND_NODVS_BUCK_VOLT = 0x15,
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BD718XX_3RD_NODVS_BUCK_VOLT = 0x16,
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BD718XX_4TH_NODVS_BUCK_VOLT = 0x17,
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BD718XX_LDO1_VOLT = 0x18,
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BD718XX_LDO2_VOLT = 0x19,
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BD718XX_LDO3_VOLT = 0x1a,
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BD718XX_LDO4_VOLT = 0x1b,
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BD718XX_LDO5_VOLT = 0x1c,
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BD718XX_LDO6_VOLT = 0x1d,
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BD71837_LDO7_VOLT = 0x1e,
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BD718XX_TRANS_COND0 = 0x1f,
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BD718XX_TRANS_COND1 = 0x20,
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BD718XX_VRFAULTEN = 0x21,
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BD718XX_MVRFLTMASK0 = 0x22,
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BD718XX_MVRFLTMASK1 = 0x23,
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BD718XX_MVRFLTMASK2 = 0x24,
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BD718XX_RCVCFG = 0x25,
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BD718XX_RCVNUM = 0x26,
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BD718XX_PWRONCONFIG0 = 0x27,
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BD718XX_PWRONCONFIG1 = 0x28,
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BD718XX_RESETSRC = 0x29,
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BD718XX_MIRQ = 0x2a,
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BD718XX_IRQ = 0x2b,
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BD718XX_IN_MON = 0x2c,
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BD718XX_POW_STATE = 0x2d,
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BD718XX_OUT32K = 0x2e,
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BD718XX_REGLOCK = 0x2f,
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BD718XX_MUXSW_EN = 0x30,
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BD718XX_REG_OTPVER = 0xff,
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BD718XX_MAX_REGISTER = 0x100,
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};
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#define BD718XX_REGLOCK_PWRSEQ 0x1
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#define BD718XX_REGLOCK_VREG 0x10
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#define BD718XX_BUCK_EN 0x01
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#define BD718XX_LDO_EN 0x40
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#define BD718XX_BUCK_SEL 0x02
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#define BD718XX_LDO_SEL 0x80
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#define DVS_BUCK_RUN_MASK 0x3f
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#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
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#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
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#define BD718XX_4TH_NODVS_BUCK_MASK 0x3f
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#define BD71847_BUCK3_MASK 0x07
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#define BD71847_BUCK3_RANGE_MASK 0xc0
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#define BD71847_BUCK4_MASK 0x03
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#define BD71847_BUCK4_RANGE_MASK 0x40
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#define BD71837_BUCK5_RANGE_MASK 0x80
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#define BD71837_BUCK6_MASK 0x03
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#define BD718XX_LDO1_MASK 0x03
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#define BD718XX_LDO1_RANGE_MASK 0x20
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#define BD718XX_LDO2_MASK 0x20
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#define BD718XX_LDO3_MASK 0x0f
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#define BD718XX_LDO4_MASK 0x0f
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#define BD718XX_LDO6_MASK 0x0f
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#define BD71837_LDO5_MASK 0x0f
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#define BD71847_LDO5_MASK 0x0f
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#define BD71847_LDO5_RANGE_MASK 0x20
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#define BD71837_LDO7_MASK 0x0f
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#endif
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