mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 14:43:49 +09:00
da409ccc4a
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
653 lines
16 KiB
C
653 lines
16 KiB
C
/*
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* TI QSPI driver
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/omap.h>
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#include <malloc.h>
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#include <spi.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include <asm/omap_common.h>
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#include <asm/ti-common/ti-edma3.h>
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#include <linux/kernel.h>
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#include <regmap.h>
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#include <syscon.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ti qpsi register bit masks */
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#define QSPI_TIMEOUT 2000000
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#define QSPI_FCLK 192000000
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#define QSPI_DRA7XX_FCLK 76800000
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#define QSPI_WLEN_MAX_BITS 128
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#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
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#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
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/* clock control */
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#define QSPI_CLK_EN BIT(31)
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#define QSPI_CLK_DIV_MAX 0xffff
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/* command */
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#define QSPI_EN_CS(n) (n << 28)
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#define QSPI_WLEN(n) ((n-1) << 19)
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#define QSPI_3_PIN BIT(18)
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#define QSPI_RD_SNGL BIT(16)
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#define QSPI_WR_SNGL (2 << 16)
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#define QSPI_INVAL (4 << 16)
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#define QSPI_RD_QUAD (7 << 16)
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/* device control */
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#define QSPI_DD(m, n) (m << (3 + n*8))
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#define QSPI_CKPHA(n) (1 << (2 + n*8))
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#define QSPI_CSPOL(n) (1 << (1 + n*8))
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#define QSPI_CKPOL(n) (1 << (n*8))
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/* status */
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#define QSPI_WC BIT(1)
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#define QSPI_BUSY BIT(0)
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#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
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#define QSPI_XFER_DONE QSPI_WC
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#define MM_SWITCH 0x01
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#define MEM_CS(cs) ((cs + 1) << 8)
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#define MEM_CS_UNSELECT 0xfffff8ff
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#define MMAP_START_ADDR_DRA 0x5c000000
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#define MMAP_START_ADDR_AM43x 0x30000000
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#define CORE_CTRL_IO 0x4a002558
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#define QSPI_CMD_READ (0x3 << 0)
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#define QSPI_CMD_READ_DUAL (0x6b << 0)
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#define QSPI_CMD_READ_QUAD (0x6c << 0)
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#define QSPI_CMD_READ_FAST (0x0b << 0)
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#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
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#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
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#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
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#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
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#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
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#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
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#define QSPI_CMD_WRITE (0x12 << 16)
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#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
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/* ti qspi register set */
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struct ti_qspi_regs {
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u32 pid;
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u32 pad0[3];
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u32 sysconfig;
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u32 pad1[3];
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u32 int_stat_raw;
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u32 int_stat_en;
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u32 int_en_set;
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u32 int_en_ctlr;
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u32 intc_eoi;
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u32 pad2[3];
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u32 clk_ctrl;
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u32 dc;
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u32 cmd;
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u32 status;
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u32 data;
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u32 setup0;
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u32 setup1;
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u32 setup2;
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u32 setup3;
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u32 memswitch;
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u32 data1;
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u32 data2;
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u32 data3;
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};
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/* ti qspi priv */
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struct ti_qspi_priv {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#else
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void *memory_map;
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uint max_hz;
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u32 num_cs;
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#endif
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struct ti_qspi_regs *base;
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void *ctrl_mod_mmap;
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ulong fclk;
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unsigned int mode;
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u32 cmd;
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u32 dc;
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};
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static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
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{
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uint clk_div;
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if (!hz)
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clk_div = 0;
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else
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clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
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/* truncate clk_div value to QSPI_CLK_DIV_MAX */
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if (clk_div > QSPI_CLK_DIV_MAX)
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clk_div = QSPI_CLK_DIV_MAX;
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debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
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/* disable SCLK */
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writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
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&priv->base->clk_ctrl);
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/* enable SCLK and program the clk divider */
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writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
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}
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static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
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{
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writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
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/* dummy readl to ensure bus sync */
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readl(&priv->base->cmd);
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}
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static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
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{
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priv->dc = 0;
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if (mode & SPI_CPHA)
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priv->dc |= QSPI_CKPHA(0);
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if (mode & SPI_CPOL)
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priv->dc |= QSPI_CKPOL(0);
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if (mode & SPI_CS_HIGH)
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priv->dc |= QSPI_CSPOL(0);
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return 0;
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}
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static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
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{
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writel(priv->dc, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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priv->dc <<= cs * 8;
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writel(priv->dc, &priv->base->dc);
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return 0;
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}
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static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
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{
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writel(0, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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}
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static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
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{
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u32 val;
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val = readl(ctrl_mod_mmap);
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if (enable)
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val |= MEM_CS(cs);
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else
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val &= MEM_CS_UNSELECT;
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writel(val, ctrl_mod_mmap);
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}
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static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags,
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u32 cs)
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{
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uint words = bitlen >> 3; /* fixed 8-bit word length */
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const uchar *txp = dout;
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uchar *rxp = din;
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uint status;
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int timeout;
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/* Setup mmap flags */
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if (flags & SPI_XFER_MMAP) {
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writel(MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
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return 0;
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} else if (flags & SPI_XFER_MMAP_END) {
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writel(~MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
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return 0;
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}
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if (bitlen == 0)
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return -1;
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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/* Setup command reg */
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priv->cmd = 0;
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priv->cmd |= QSPI_WLEN(8);
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priv->cmd |= QSPI_EN_CS(cs);
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if (priv->mode & SPI_3WIRE)
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priv->cmd |= QSPI_3_PIN;
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priv->cmd |= 0xfff;
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while (words) {
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u8 xfer_len = 0;
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if (txp) {
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u32 cmd = priv->cmd;
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if (words >= QSPI_WLEN_MAX_BYTES) {
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u32 *txbuf = (u32 *)txp;
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u32 data;
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data3);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data2);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data1);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data);
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cmd &= ~QSPI_WLEN_MASK;
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cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
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xfer_len = QSPI_WLEN_MAX_BYTES;
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} else {
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writeb(*txp, &priv->base->data);
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xfer_len = 1;
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}
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debug("tx cmd %08x dc %08x\n",
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cmd | QSPI_WR_SNGL, priv->dc);
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writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
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status = readl(&priv->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: TX timeout!\n");
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return -1;
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}
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status = readl(&priv->base->status);
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}
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txp += xfer_len;
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debug("tx done, status %08x\n", status);
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}
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if (rxp) {
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debug("rx cmd %08x dc %08x\n",
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((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
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writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
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status = readl(&priv->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: RX timeout!\n");
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return -1;
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}
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status = readl(&priv->base->status);
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}
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*rxp++ = readl(&priv->base->data);
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xfer_len = 1;
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debug("rx done, status %08x, read %02x\n",
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status, *(rxp-1));
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}
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words -= xfer_len;
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}
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/* Terminate frame */
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if (flags & SPI_XFER_END)
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ti_qspi_cs_deactivate(priv);
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return 0;
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}
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/* TODO: control from sf layer to here through dm-spi */
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#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
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void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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{
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unsigned int addr = (unsigned int) (data);
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unsigned int edma_slot_num = 1;
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
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/* enable edma3 clocks */
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enable_edma3_clocks();
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/* Call edma3 api to do actual DMA transfer */
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edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
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/* disable edma3 clocks */
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disable_edma3_clocks();
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*((unsigned int *)offset) += len;
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}
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#endif
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#ifndef CONFIG_DM_SPI
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static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
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{
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return container_of(slave, struct ti_qspi_priv, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* CS handled in xfer */
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return;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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ti_qspi_cs_deactivate(priv);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
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{
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u32 memval = 0;
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#ifdef CONFIG_QSPI_QUAD_SUPPORT
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struct spi_slave *slave = &priv->slave;
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memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_8_BITS |
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QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS);
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slave->mode |= SPI_RX_QUAD;
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#else
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
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QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS;
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#endif
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writel(memval, &priv->base->setup0);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ti_qspi_priv *priv;
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#ifdef CONFIG_AM43XX
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
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#endif
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priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
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if (!priv) {
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printf("SPI_error: Fail to allocate ti_qspi_priv\n");
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return NULL;
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}
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priv->base = (struct ti_qspi_regs *)QSPI_BASE;
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priv->mode = mode;
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#if defined(CONFIG_DRA7XX)
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priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
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priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
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priv->fclk = QSPI_DRA7XX_FCLK;
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#else
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priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
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priv->fclk = QSPI_FCLK;
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#endif
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ti_spi_set_speed(priv, max_hz);
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#ifdef CONFIG_TI_SPI_MMAP
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ti_spi_setup_spi_register(priv);
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#endif
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return &priv->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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free(priv);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_set_mode(priv, priv->mode);
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return __ti_qspi_claim_bus(priv, priv->slave.cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_release_bus(priv);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
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priv->slave.bus, priv->slave.cs, bitlen, flags);
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return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
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}
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#else /* CONFIG_DM_SPI */
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static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
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struct spi_slave *slave,
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bool enable)
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{
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u32 memval;
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u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
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if (!enable) {
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writel(0, &priv->base->setup0);
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return;
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}
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memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
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switch (mode) {
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case SPI_RX_QUAD:
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memval |= QSPI_CMD_READ_QUAD;
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memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
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memval |= QSPI_SETUP0_READ_QUAD;
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slave->mode |= SPI_RX_QUAD;
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break;
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case SPI_RX_DUAL:
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memval |= QSPI_CMD_READ_DUAL;
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memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
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memval |= QSPI_SETUP0_READ_DUAL;
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break;
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default:
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memval |= QSPI_CMD_READ;
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memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
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memval |= QSPI_SETUP0_READ_NORMAL;
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break;
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}
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writel(memval, &priv->base->setup0);
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}
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static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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ti_spi_set_speed(priv, max_hz);
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return 0;
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}
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|
|
|
static int ti_qspi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
return __ti_qspi_set_mode(priv, mode);
|
|
}
|
|
|
|
static int ti_qspi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
struct ti_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
|
|
if (slave_plat->cs > priv->num_cs) {
|
|
debug("invalid qspi chip select\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
__ti_qspi_setup_memorymap(priv, slave, true);
|
|
|
|
return __ti_qspi_claim_bus(priv, slave_plat->cs);
|
|
}
|
|
|
|
static int ti_qspi_release_bus(struct udevice *dev)
|
|
{
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
struct ti_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
|
|
__ti_qspi_setup_memorymap(priv, slave, false);
|
|
__ti_qspi_release_bus(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
|
|
struct ti_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
|
|
if (slave->cs > priv->num_cs) {
|
|
debug("invalid qspi chip select\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
|
|
}
|
|
|
|
static int ti_qspi_probe(struct udevice *bus)
|
|
{
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->fclk = dev_get_driver_data(bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *map_syscon_chipselects(struct udevice *bus)
|
|
{
|
|
#if CONFIG_IS_ENABLED(SYSCON)
|
|
struct udevice *syscon;
|
|
struct regmap *regmap;
|
|
const fdt32_t *cell;
|
|
int len, err;
|
|
|
|
err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
|
|
"syscon-chipselects", &syscon);
|
|
if (err) {
|
|
debug("%s: unable to find syscon device (%d)\n", __func__,
|
|
err);
|
|
return NULL;
|
|
}
|
|
|
|
regmap = syscon_get_regmap(syscon);
|
|
if (IS_ERR(regmap)) {
|
|
debug("%s: unable to find regmap (%ld)\n", __func__,
|
|
PTR_ERR(regmap));
|
|
return NULL;
|
|
}
|
|
|
|
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
|
|
"syscon-chipselects", &len);
|
|
if (len < 2*sizeof(fdt32_t)) {
|
|
debug("%s: offset not available\n", __func__);
|
|
return NULL;
|
|
}
|
|
|
|
return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
|
|
#else
|
|
fdt_addr_t addr;
|
|
addr = devfdt_get_addr_index(bus, 2);
|
|
return (addr == FDT_ADDR_T_NONE) ? NULL :
|
|
map_physmem(addr, 0, MAP_NOCACHE);
|
|
#endif
|
|
}
|
|
|
|
static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
|
|
{
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev_of_offset(bus);
|
|
|
|
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
|
|
priv->base = map_physmem(devfdt_get_addr(bus),
|
|
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
|
|
priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
|
|
MAP_NOCACHE);
|
|
|
|
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
|
|
if (priv->max_hz < 0) {
|
|
debug("Error: Max frequency missing\n");
|
|
return -ENODEV;
|
|
}
|
|
priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
|
|
|
|
debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
|
|
(int)priv->base, priv->max_hz);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ti_qspi_child_pre_probe(struct udevice *dev)
|
|
{
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
slave->memory_map = priv->memory_map;
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops ti_qspi_ops = {
|
|
.claim_bus = ti_qspi_claim_bus,
|
|
.release_bus = ti_qspi_release_bus,
|
|
.xfer = ti_qspi_xfer,
|
|
.set_speed = ti_qspi_set_speed,
|
|
.set_mode = ti_qspi_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id ti_qspi_ids[] = {
|
|
{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
|
|
{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ti_qspi) = {
|
|
.name = "ti_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = ti_qspi_ids,
|
|
.ops = &ti_qspi_ops,
|
|
.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
|
|
.probe = ti_qspi_probe,
|
|
.child_pre_probe = ti_qspi_child_pre_probe,
|
|
};
|
|
#endif /* CONFIG_DM_SPI */
|