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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 14:43:49 +09:00
![Fabio Estevam](/assets/img/avatar_default.png)
Latest wandboard hardware revision is revd1, which brings the following new features: - PFUZE100 PMIC - AR8035 Ethernet PHY - Upgrade Wifi/BT chip to BCM4339/BCM43430. The detection mechanism is to probe the PMIC and when it is found, then the revision of the board is revd1. As the detection is done via PMIC, we need to print the board version at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier. Make the necessary adjustments for the AR8035 PHY to work on revd1. Based on Richard Hu's work from Technexion's U-Boot tree. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
562 lines
14 KiB
C
562 lines
14 KiB
C
/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2014 O.S. Systems Software LTDA.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <asm/mach-imx/sata.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <phy.h>
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#include <input.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
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#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
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#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
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#define REV_DETECTION IMX_GPIO_NR(2, 28)
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static bool with_pmic;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* Carrier MicroSD Card Detect */
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* SOM MicroSD Card Detect */
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IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8031 PHY Reset */
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IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
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/* AR8035 POWER */
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IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const rev_detection_pad[] = {
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IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart1_pads);
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}
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static void setup_iomux_enet(void)
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{
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SETUP_IOMUX_PADS(enet_pads);
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if (with_pmic) {
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SETUP_IOMUX_PADS(enet_ar8035_power_pads);
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/* enable AR8035 POWER */
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gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
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}
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/* wait until 3.3V of PHY and clock become stable */
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mdelay(10);
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/* Reset AR8031 PHY */
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gpio_direction_output(ETH_PHY_RESET, 0);
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mdelay(10);
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gpio_set_value(ETH_PHY_RESET, 1);
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udelay(100);
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}
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC3_BASE_ADDR},
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{USDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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u32 index = 0;
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/*
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* Following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 SOM MicroSD
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* mmc1 Carrier board MicroSD
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*/
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
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switch (index) {
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case 0:
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SETUP_IOMUX_PADS(usdhc3_pads);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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gpio_direction_input(USDHC3_CD_GPIO);
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break;
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case 1:
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SETUP_IOMUX_PADS(usdhc1_pads);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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gpio_direction_input(USDHC1_CD_GPIO);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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index + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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int mask;
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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if (with_pmic)
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mask = 0xffe7; /* AR8035 */
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else
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mask = 0xffe3; /* AR8031 */
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val &= mask;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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struct i2c_pads_info mx6q_i2c2_pad_info = {
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.scl = {
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.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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struct i2c_pads_info mx6dl_i2c2_pad_info = {
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.scl = {
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.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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struct i2c_pads_info mx6q_i2c3_pad_info = {
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.scl = {
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.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 5)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(7, 11)
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}
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};
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struct i2c_pads_info mx6dl_i2c3_pad_info = {
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.scl = {
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.i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 5)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(7, 11)
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}
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};
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static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
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IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
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};
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static int detect_i2c(struct display_info_t const *dev)
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{
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return (0 == i2c_set_bus_num(dev->bus)) &&
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(0 == i2c_probe(dev->addr));
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}
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static void enable_fwadapt_7wvga(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
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gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
|
|
.xres = 1024,
|
|
.yres = 768,
|
|
.pixclock = 15385,
|
|
.left_margin = 220,
|
|
.right_margin = 40,
|
|
.upper_margin = 21,
|
|
.lower_margin = 7,
|
|
.hsync_len = 60,
|
|
.vsync_len = 10,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} }, {
|
|
.bus = 1,
|
|
.addr = 0x10,
|
|
.pixfmt = IPU_PIX_FMT_RGB666,
|
|
.detect = detect_i2c,
|
|
.enable = enable_fwadapt_7wvga,
|
|
.mode = {
|
|
.name = "FWBADAPT-LCD-F07A-0102",
|
|
.refresh = 60,
|
|
.xres = 800,
|
|
.yres = 480,
|
|
.pixclock = 33260,
|
|
.left_margin = 128,
|
|
.right_margin = 128,
|
|
.upper_margin = 22,
|
|
.lower_margin = 22,
|
|
.hsync_len = 1,
|
|
.vsync_len = 1,
|
|
.sync = 0,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} } };
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
|
|
static void setup_display(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
int reg;
|
|
|
|
enable_ipu_clock();
|
|
imx_setup_hdmi();
|
|
|
|
reg = readl(&mxc_ccm->chsccdr);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->chsccdr);
|
|
|
|
/* Disable LCD backlight */
|
|
SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
|
|
gpio_direction_input(IMX_GPIO_NR(4, 20));
|
|
}
|
|
#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
setup_iomux_enet();
|
|
|
|
return cpu_eth_init(bis);
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
#ifdef CONFIG_SATA
|
|
/* Only mx6q wandboard has SATA */
|
|
if (is_cpu_type(MXC_CPU_MX6Q))
|
|
setup_sata();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define PMIC_I2C_BUS 2
|
|
|
|
int power_init_board(void)
|
|
{
|
|
struct pmic *p;
|
|
u32 reg;
|
|
|
|
/* configure PFUZE100 PMIC */
|
|
power_pfuze100_init(PMIC_I2C_BUS);
|
|
p = pmic_get("PFUZE100");
|
|
if (p && !pmic_probe(p)) {
|
|
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
|
|
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
|
|
with_pmic = true;
|
|
|
|
/* Set VGEN2 to 1.5V and enable */
|
|
pmic_reg_read(p, PFUZE100_VGEN2VOL, ®);
|
|
reg &= ~(LDO_VOL_MASK);
|
|
reg |= (LDOA_1_50V | (1 << (LDO_EN)));
|
|
pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Do not overwrite the console
|
|
* Use always serial for U-Boot console
|
|
*/
|
|
int overwrite_console(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
static bool is_revc1(void)
|
|
{
|
|
SETUP_IOMUX_PADS(rev_detection_pad);
|
|
gpio_direction_input(REV_DETECTION);
|
|
|
|
if (gpio_get_value(REV_DETECTION))
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
static bool is_revd1(void)
|
|
{
|
|
if (with_pmic)
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
if (is_mx6dq())
|
|
env_set("board_rev", "MX6Q");
|
|
else
|
|
env_set("board_rev", "MX6DL");
|
|
|
|
if (is_revd1())
|
|
env_set("board_name", "D1");
|
|
else if (is_revc1())
|
|
env_set("board_name", "C1");
|
|
else
|
|
env_set("board_name", "B1");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
|
|
if (is_mx6dq()) {
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
|
|
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
|
|
} else {
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
|
|
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
|
|
}
|
|
|
|
setup_display();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
if (is_revd1())
|
|
puts("Board: Wandboard rev D1\n");
|
|
else if (is_revc1())
|
|
puts("Board: Wandboard rev C1\n");
|
|
else
|
|
puts("Board: Wandboard rev B1\n");
|
|
|
|
return 0;
|
|
}
|