mirror of
https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
Since commit 0e7368c6c4
(kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
230 lines
4.8 KiB
C
230 lines
4.8 KiB
C
/*
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* Copyright (C) 2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/ddrphy-regs.h>
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/* Select either decimal or hexadecimal */
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#if 1
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#define PRINTF_FORMAT "%2d"
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#else
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#define PRINTF_FORMAT "%02x"
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#endif
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/* field separator */
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#define FS " "
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static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
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{
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return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
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}
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static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
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{
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int ch, p, dx;
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struct ddrphy __iomem *phy;
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for (ch = 0; ch < NR_DDRCH; ch++) {
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for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
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phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
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for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
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printf("CH%dP%dDX%d:", ch, p, dx);
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(*callback)(&phy->dx[dx]);
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printf("\n");
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}
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}
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}
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}
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static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
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{
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int i;
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for (i = 0; i < 10; i++)
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printf(FS PRINTF_FORMAT, read_bdl(dx, i));
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printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
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}
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void wbdl_dump(void)
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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dump_loop(&__wbdl_dump);
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}
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static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
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{
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int i;
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for (i = 15; i < 24; i++)
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printf(FS PRINTF_FORMAT, read_bdl(dx, i));
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printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
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}
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void rbdl_dump(void)
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
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dump_loop(&__rbdl_dump);
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}
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static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
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{
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int rank;
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u32 lcdlr0 = readl(&dx->lcdlr[0]);
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u32 gtr = readl(&dx->gtr);
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for (rank = 0; rank < 4; rank++) {
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u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
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u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
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printf(FS PRINTF_FORMAT "%sT", wld,
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wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
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}
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}
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void wld_dump(void)
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__wld_dump);
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}
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static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
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{
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int rank;
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u32 lcdlr2 = readl(&dx->lcdlr[2]);
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u32 gtr = readl(&dx->gtr);
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for (rank = 0; rank < 4; rank++) {
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u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
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u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
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printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
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}
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}
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void dqsgd_dump(void)
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__dqsgd_dump);
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}
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static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
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{
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int i;
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u32 mdl = readl(&dx->mdlr);
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for (i = 0; i < 3; i++)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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void mdl_dump(void)
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{
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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dump_loop(&__mdl_dump);
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}
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#define REG_DUMP(x) \
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{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
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p - (u32 *)phy, #x, p, readl(p)); }
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void reg_dump(void)
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{
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int ch, p;
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struct ddrphy __iomem *phy;
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printf("\n--- DDR PHY registers ---\n");
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for (ch = 0; ch < NR_DDRCH; ch++) {
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for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
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printf("== Ch%d, PHY%d ==\n", ch, p);
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printf(" No: Name : Address : Data\n");
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phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
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REG_DUMP(ridr);
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REG_DUMP(pir);
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REG_DUMP(pgcr[0]);
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REG_DUMP(pgcr[1]);
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REG_DUMP(pgsr[0]);
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REG_DUMP(pgsr[1]);
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REG_DUMP(pllcr);
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REG_DUMP(ptr[0]);
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REG_DUMP(ptr[1]);
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REG_DUMP(ptr[2]);
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REG_DUMP(ptr[3]);
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REG_DUMP(ptr[4]);
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REG_DUMP(acmdlr);
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REG_DUMP(acbdlr);
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REG_DUMP(dxccr);
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REG_DUMP(dsgcr);
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REG_DUMP(dcr);
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REG_DUMP(dtpr[0]);
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REG_DUMP(dtpr[1]);
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REG_DUMP(dtpr[2]);
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REG_DUMP(mr0);
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REG_DUMP(mr1);
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REG_DUMP(mr2);
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REG_DUMP(mr3);
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REG_DUMP(dx[0].gcr);
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REG_DUMP(dx[0].gtr);
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REG_DUMP(dx[1].gcr);
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REG_DUMP(dx[1].gtr);
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}
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}
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}
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static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *cmd = argv[1];
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if (argc == 1)
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cmd = "all";
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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wbdl_dump();
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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rbdl_dump();
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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wld_dump();
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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dqsgd_dump();
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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mdl_dump();
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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reg_dump();
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return 0;
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}
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U_BOOT_CMD(
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ddr, 2, 1, do_ddr,
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"UniPhier DDR PHY parameters dumper",
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"- dump all of the followings\n"
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"ddr wbdl - dump Write Bit Delay\n"
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"ddr rbdl - dump Read Bit Delay\n"
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"ddr wld - dump Write Leveling\n"
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"ddr dqsgd - dump DQS Gating Delay\n"
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"ddr mdl - dump Master Delay Line\n"
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"ddr reg - dump registers\n"
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);
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