mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
![Stephen Warren](/assets/img/avatar_default.png)
When the CPU is in non-secure (NS) mode (when running U-Boot under a secure monitor), certain actions cannot be taken, since they would need to write to secure-only registers. One example is configuring the ARM architectural timer's CNTFRQ register. We could support this in one of two ways: 1) Compile twice, once for secure mode (in which case anything goes) and once for non-secure mode (in which case certain actions are disabled). This complicates things, since everyone needs to keep track of different U-Boot binaries for different situations. 2) Detect NS mode at run-time, and optionally skip any impossible actions. This has the advantage of a single U-Boot binary working in all cases. (2) is not possible on ARM in general, since there's no architectural way to detect secure-vs-non-secure. However, there is a Tegra-specific way to detect this. This patches uses that feature to detect secure vs. NS mode on Tegra, and uses that to: * Skip the ARM arch timer initialization. * Set/clear an environment variable so that boot scripts can take different action depending on which mode the CPU is in. This might be something like: if CPU is secure: load secure monitor code into RAM. boot secure monitor. secure monitor will restart (a new copy of) U-Boot in NS mode. else: execute normal boot process Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
674 lines
18 KiB
C
674 lines
18 KiB
C
/*
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* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Tegra SoC common clock control functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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#include <div64.h>
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#include <fdtdec.h>
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/*
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* This is our record of the current clock rate of each clock. We don't
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* fill all of these in since we are only really interested in clocks which
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* we use as parents.
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*/
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static unsigned pll_rate[CLOCK_ID_COUNT];
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/*
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* The oscillator frequency is fixed to one of four set values. Based on this
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* the other clocks are set up appropriately.
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*/
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static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
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13000000,
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19200000,
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12000000,
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26000000,
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};
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/* return 1 if a peripheral ID is in range */
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#define clock_type_id_isvalid(id) ((id) >= 0 && \
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(id) < CLOCK_TYPE_COUNT)
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char pllp_valid = 1; /* PLLP is set up correctly */
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/* return 1 if a periphc_internal_id is in range */
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#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
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(id) < PERIPHC_COUNT)
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/* number of clock outputs of a PLL */
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static const u8 pll_num_clkouts[] = {
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1, /* PLLC */
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1, /* PLLM */
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4, /* PLLP */
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1, /* PLLA */
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0, /* PLLU */
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0, /* PLLD */
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};
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int clock_get_osc_bypass(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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reg = readl(&clkrst->crc_osc_ctrl);
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return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
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}
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/* Returns a pointer to the registers of the given pll */
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static struct clk_pll *get_pll(enum clock_id clkid)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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assert(clock_id_is_pll(clkid));
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return &clkrst->crc_pll[clkid];
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}
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int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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u32 *divp, u32 *cpcon, u32 *lfcon)
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{
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struct clk_pll *pll = get_pll(clkid);
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u32 data;
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assert(clkid != CLOCK_ID_USB);
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/* Safety check, adds to code size but is small */
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if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
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return -1;
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data = readl(&pll->pll_base);
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*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
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*divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
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*divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
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data = readl(&pll->pll_misc);
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*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
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*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
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return 0;
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}
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unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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u32 divp, u32 cpcon, u32 lfcon)
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{
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struct clk_pll *pll = get_pll(clkid);
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u32 data;
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/*
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* We cheat by treating all PLL (except PLLU) in the same fashion.
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* This works only because:
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* - same fields are always mapped at same offsets, except DCCON
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* - DCCON is always 0, doesn't conflict
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* - M,N, P of PLLP values are ignored for PLLP
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*/
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data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
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writel(data, &pll->pll_misc);
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data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
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(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
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if (clkid == CLOCK_ID_USB)
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data |= divp << PLLU_VCO_FREQ_SHIFT;
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else
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data |= divp << PLL_DIVP_SHIFT;
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writel(data, &pll->pll_base);
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/* calculate the stable time */
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return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
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}
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void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
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unsigned divisor)
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{
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u32 *reg = get_periph_source_reg(periph_id);
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u32 value;
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value = readl(reg);
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value &= ~OUT_CLK_SOURCE_31_30_MASK;
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value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
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value &= ~OUT_CLK_DIVISOR_MASK;
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value |= divisor << OUT_CLK_DIVISOR_SHIFT;
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writel(value, reg);
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}
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void clock_ll_set_source(enum periph_id periph_id, unsigned source)
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{
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u32 *reg = get_periph_source_reg(periph_id);
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
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source << OUT_CLK_SOURCE_31_30_SHIFT);
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}
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/**
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* Given the parent's rate and the required rate for the children, this works
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* out the peripheral clock divider to use, in 7.1 binary format.
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*
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* @param divider_bits number of divider bits (8 or 16)
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* @param parent_rate clock rate of parent clock in Hz
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* @param rate required clock rate for this clock
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* @return divider which should be used
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*/
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static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
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unsigned long rate)
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{
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u64 divider = parent_rate * 2;
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unsigned max_divider = 1 << divider_bits;
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divider += rate - 1;
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do_div(divider, rate);
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if ((s64)divider - 2 < 0)
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return 0;
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if ((s64)divider - 2 >= max_divider)
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return -1;
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return divider - 2;
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}
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int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
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{
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struct clk_pll *pll = get_pll(clkid);
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int data = 0, div = 0, offset = 0;
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if (!clock_id_is_pll(clkid))
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return -1;
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if (pllout + 1 > pll_num_clkouts[clkid])
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return -1;
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div = clk_get_divider(8, pll_rate[clkid], rate);
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if (div < 0)
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return -1;
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/* out2 and out4 are in the high part of the register */
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if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
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offset = 16;
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data = (div << PLL_OUT_RATIO_SHIFT) |
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PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
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clrsetbits_le32(&pll->pll_out[pllout >> 1],
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PLL_OUT_RATIO_MASK << offset, data << offset);
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return 0;
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}
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/**
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* Given the parent's rate and the divider in 7.1 format, this works out the
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* resulting peripheral clock rate.
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*
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* @param parent_rate clock rate of parent clock in Hz
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* @param divider which should be used in 7.1 format
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* @return effective clock rate of peripheral
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*/
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static unsigned long get_rate_from_divider(unsigned long parent_rate,
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int divider)
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{
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u64 rate;
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rate = (u64)parent_rate * 2;
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do_div(rate, divider + 2);
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return rate;
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}
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unsigned long clock_get_periph_rate(enum periph_id periph_id,
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enum clock_id parent)
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{
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u32 *reg = get_periph_source_reg(periph_id);
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return get_rate_from_divider(pll_rate[parent],
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(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
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}
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/**
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* Find the best available 7.1 format divisor given a parent clock rate and
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* required child clock rate. This function assumes that a second-stage
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* divisor is available which can divide by powers of 2 from 1 to 256.
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*
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* @param divider_bits number of divider bits (8 or 16)
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* @param parent_rate clock rate of parent clock in Hz
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* @param rate required clock rate for this clock
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* @param extra_div value for the second-stage divisor (not set if this
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* function returns -1.
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* @return divider which should be used, or -1 if nothing is valid
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*
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*/
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static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
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unsigned long rate, int *extra_div)
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{
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int shift;
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int best_divider = -1;
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int best_error = rate;
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/* try dividers from 1 to 256 and find closest match */
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for (shift = 0; shift <= 8 && best_error > 0; shift++) {
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unsigned divided_parent = parent_rate >> shift;
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int divider = clk_get_divider(divider_bits, divided_parent,
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rate);
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unsigned effective_rate = get_rate_from_divider(divided_parent,
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divider);
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int error = rate - effective_rate;
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/* Given a valid divider, look for the lowest error */
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if (divider != -1 && error < best_error) {
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best_error = error;
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*extra_div = 1 << shift;
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best_divider = divider;
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}
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}
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/* return what we found - *extra_div will already be set */
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return best_divider;
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}
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/**
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* Adjust peripheral PLL to use the given divider and source.
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*
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* @param periph_id peripheral to adjust
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* @param source Source number (0-3 or 0-7)
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* @param mux_bits Number of mux bits (2 or 4)
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* @param divider Required divider in 7.1 or 15.1 format
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* @return 0 if ok, -1 on error (requesting a parent clock which is not valid
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* for this peripheral)
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*/
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static int adjust_periph_pll(enum periph_id periph_id, int source,
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int mux_bits, unsigned divider)
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{
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u32 *reg = get_periph_source_reg(periph_id);
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clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
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divider << OUT_CLK_DIVISOR_SHIFT);
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udelay(1);
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/* work out the source clock and set it */
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if (source < 0)
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return -1;
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switch (mux_bits) {
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case MASK_BITS_31_30:
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
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source << OUT_CLK_SOURCE_31_30_SHIFT);
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break;
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case MASK_BITS_31_29:
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
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source << OUT_CLK_SOURCE_31_29_SHIFT);
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break;
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case MASK_BITS_31_28:
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
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source << OUT_CLK_SOURCE_31_28_SHIFT);
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break;
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default:
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return -1;
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}
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udelay(2);
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return 0;
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}
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unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
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enum clock_id parent, unsigned rate, int *extra_div)
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{
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unsigned effective_rate;
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int mux_bits, divider_bits, source;
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int divider;
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int xdiv = 0;
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/* work out the source clock and set it */
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source = get_periph_clock_source(periph_id, parent, &mux_bits,
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÷r_bits);
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divider = find_best_divider(divider_bits, pll_rate[parent],
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rate, &xdiv);
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if (extra_div)
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*extra_div = xdiv;
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assert(divider >= 0);
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if (adjust_periph_pll(periph_id, source, mux_bits, divider))
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return -1U;
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debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
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get_periph_source_reg(periph_id),
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readl(get_periph_source_reg(periph_id)));
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/* Check what we ended up with. This shouldn't matter though */
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effective_rate = clock_get_periph_rate(periph_id, parent);
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if (extra_div)
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effective_rate /= *extra_div;
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if (rate != effective_rate)
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debug("Requested clock rate %u not honored (got %u)\n",
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rate, effective_rate);
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return effective_rate;
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}
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unsigned clock_start_periph_pll(enum periph_id periph_id,
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enum clock_id parent, unsigned rate)
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{
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unsigned effective_rate;
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reset_set_enable(periph_id, 1);
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clock_enable(periph_id);
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effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
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NULL);
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reset_set_enable(periph_id, 0);
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return effective_rate;
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}
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void clock_enable(enum periph_id clkid)
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{
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clock_set_enable(clkid, 1);
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}
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void clock_disable(enum periph_id clkid)
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{
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clock_set_enable(clkid, 0);
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}
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void reset_periph(enum periph_id periph_id, int us_delay)
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{
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/* Put peripheral into reset */
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reset_set_enable(periph_id, 1);
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udelay(us_delay);
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/* Remove reset */
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reset_set_enable(periph_id, 0);
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udelay(us_delay);
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}
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void reset_cmplx_set_enable(int cpu, int which, int reset)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 mask;
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/* Form the mask, which depends on the cpu chosen (2 or 4) */
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assert(cpu >= 0 && cpu < MAX_NUM_CPU);
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mask = which << cpu;
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/* either enable or disable those reset for that CPU */
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if (reset)
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writel(mask, &clkrst->crc_cpu_cmplx_set);
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else
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writel(mask, &clkrst->crc_cpu_cmplx_clr);
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}
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unsigned clock_get_rate(enum clock_id clkid)
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{
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struct clk_pll *pll;
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u32 base;
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u32 divm;
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u64 parent_rate;
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u64 rate;
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parent_rate = osc_freq[clock_get_osc_freq()];
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if (clkid == CLOCK_ID_OSC)
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return parent_rate;
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pll = get_pll(clkid);
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base = readl(&pll->pll_base);
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/* Oh for bf_unpack()... */
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rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
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divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
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if (clkid == CLOCK_ID_USB)
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divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
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else
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divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
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do_div(rate, divm);
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return rate;
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}
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/**
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* Set the output frequency you want for each PLL clock.
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* PLL output frequencies are programmed by setting their N, M and P values.
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* The governing equations are:
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* VCO = (Fi / m) * n, Fo = VCO / (2^p)
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* where Fo is the output frequency from the PLL.
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* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
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* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
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* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
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*
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* @param n PLL feedback divider(DIVN)
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* @param m PLL input divider(DIVN)
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* @param p post divider(DIVP)
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* @param cpcon base PLL charge pump(CPCON)
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* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
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* be overriden), 1 if PLL is already correct
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*/
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int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
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{
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u32 base_reg;
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u32 misc_reg;
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struct clk_pll *pll;
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pll = get_pll(clkid);
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base_reg = readl(&pll->pll_base);
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/* Set BYPASS, m, n and p to PLL_BASE */
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base_reg &= ~PLL_DIVM_MASK;
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base_reg |= m << PLL_DIVM_SHIFT;
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|
|
base_reg &= ~PLL_DIVN_MASK;
|
|
base_reg |= n << PLL_DIVN_SHIFT;
|
|
|
|
base_reg &= ~PLL_DIVP_MASK;
|
|
base_reg |= p << PLL_DIVP_SHIFT;
|
|
|
|
if (clkid == CLOCK_ID_PERIPH) {
|
|
/*
|
|
* If the PLL is already set up, check that it is correct
|
|
* and record this info for clock_verify() to check.
|
|
*/
|
|
if (base_reg & PLL_BASE_OVRRIDE_MASK) {
|
|
base_reg |= PLL_ENABLE_MASK;
|
|
if (base_reg != readl(&pll->pll_base))
|
|
pllp_valid = 0;
|
|
return pllp_valid ? 1 : -1;
|
|
}
|
|
base_reg |= PLL_BASE_OVRRIDE_MASK;
|
|
}
|
|
|
|
base_reg |= PLL_BYPASS_MASK;
|
|
writel(base_reg, &pll->pll_base);
|
|
|
|
/* Set cpcon to PLL_MISC */
|
|
misc_reg = readl(&pll->pll_misc);
|
|
misc_reg &= ~PLL_CPCON_MASK;
|
|
misc_reg |= cpcon << PLL_CPCON_SHIFT;
|
|
writel(misc_reg, &pll->pll_misc);
|
|
|
|
/* Enable PLL */
|
|
base_reg |= PLL_ENABLE_MASK;
|
|
writel(base_reg, &pll->pll_base);
|
|
|
|
/* Disable BYPASS */
|
|
base_reg &= ~PLL_BYPASS_MASK;
|
|
writel(base_reg, &pll->pll_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void clock_ll_start_uart(enum periph_id periph_id)
|
|
{
|
|
/* Assert UART reset and enable clock */
|
|
reset_set_enable(periph_id, 1);
|
|
clock_enable(periph_id);
|
|
clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
|
|
|
|
/* wait for 2us */
|
|
udelay(2);
|
|
|
|
/* De-assert reset to UART */
|
|
reset_set_enable(periph_id, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_CONTROL
|
|
int clock_decode_periph_id(const void *blob, int node)
|
|
{
|
|
enum periph_id id;
|
|
u32 cell[2];
|
|
int err;
|
|
|
|
err = fdtdec_get_int_array(blob, node, "clocks", cell,
|
|
ARRAY_SIZE(cell));
|
|
if (err)
|
|
return -1;
|
|
id = clk_id_to_periph_id(cell[1]);
|
|
assert(clock_periph_id_isvalid(id));
|
|
return id;
|
|
}
|
|
#endif /* CONFIG_OF_CONTROL */
|
|
|
|
int clock_verify(void)
|
|
{
|
|
struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
|
|
u32 reg = readl(&pll->pll_base);
|
|
|
|
if (!pllp_valid) {
|
|
printf("Warning: PLLP %x is not correct\n", reg);
|
|
return -1;
|
|
}
|
|
debug("PLLP %x is correct\n", reg);
|
|
return 0;
|
|
}
|
|
|
|
void clock_init(void)
|
|
{
|
|
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
|
|
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
|
|
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
|
|
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
|
|
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
|
|
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
|
|
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
|
|
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
|
|
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
|
|
debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
|
|
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
|
|
|
|
/* Do any special system timer/TSC setup */
|
|
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
|
|
if (!tegra_cpu_is_non_secure())
|
|
#endif
|
|
arch_timer_init();
|
|
}
|
|
|
|
static void set_avp_clock_source(u32 src)
|
|
{
|
|
struct clk_rst_ctlr *clkrst =
|
|
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
|
u32 val;
|
|
|
|
val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
|
|
(src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
|
|
(src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
|
|
(src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
|
|
(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
|
|
writel(val, &clkrst->crc_sclk_brst_pol);
|
|
udelay(3);
|
|
}
|
|
|
|
/*
|
|
* This function is useful on Tegra30, and any later SoCs that have compatible
|
|
* PLLP configuration registers.
|
|
*/
|
|
void tegra30_set_up_pllp(void)
|
|
{
|
|
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
|
u32 reg;
|
|
|
|
/*
|
|
* Based on the Tegra TRM, the system clock (which is the AVP clock) can
|
|
* run up to 275MHz. On power on, the default sytem clock source is set
|
|
* to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
|
|
* 408MHz which is beyond system clock's upper limit.
|
|
*
|
|
* The fix is to set the system clock to CLK_M before initializing PLLP,
|
|
* and then switch back to PLLP_OUT4, which has an appropriate divider
|
|
* configured, after PLLP has been configured
|
|
*/
|
|
set_avp_clock_source(SCLK_SOURCE_CLKM);
|
|
|
|
/*
|
|
* PLLP output frequency set to 408Mhz
|
|
* PLLC output frequency set to 228Mhz
|
|
*/
|
|
switch (clock_get_osc_freq()) {
|
|
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
|
|
break;
|
|
case CLOCK_OSC_FREQ_19_2:
|
|
default:
|
|
/*
|
|
* These are not supported. It is too early to print a
|
|
* message and the UART likely won't work anyway due to the
|
|
* oscillator being wrong.
|
|
*/
|
|
break;
|
|
}
|
|
|
|
/* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
|
|
|
|
/* OUT1, 2 */
|
|
/* Assert RSTN before enable */
|
|
reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
|
|
writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
|
|
/* Set divisor and reenable */
|
|
reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
|
|
| PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
|
|
| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
|
|
| PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
|
|
writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
|
|
|
|
/* OUT3, 4 */
|
|
/* Assert RSTN before enable */
|
|
reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
|
|
writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
|
|
/* Set divisor and reenable */
|
|
reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
|
|
| PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
|
|
| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
|
|
| PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
|
|
writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
|
|
|
|
set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
|
|
}
|