mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
cdb6babec6
So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
228 lines
5.0 KiB
Plaintext
228 lines
5.0 KiB
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Intel Crown Bay";
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compatible = "intel,crownbay", "intel,queensbay";
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aliases {
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spi0 = "/spi";
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};
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config {
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silent_console = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <1>;
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intel,apic-id = <1>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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chosen {
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/*
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* By default the legacy superio serial port is used as the
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* U-Boot serial console. If we want to use UART from Topcliff
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* PCH as the console, change this property to &pciuart#.
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*
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* For example, stdout-path = &pciuart0 will use the first
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* UART on Topcliff PCH.
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*/
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stdout-path = "/serial";
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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reg = <0>;
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compatible = "sst,25vf016b", "spi-flash";
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memory-map = <0xffe00000 0x00200000>;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m0220661105_cv.dtsi"
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};
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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pcie@17,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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topcliff@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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pciuart0: uart@a,1 {
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compatible = "pci8086,8811.00",
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"pci8086,8811",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025100 0x0 0x0 0x0 0x0
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0x01025110 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart1: uart@a,2 {
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compatible = "pci8086,8812.00",
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"pci8086,8812",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025200 0x0 0x0 0x0 0x0
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0x01025210 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart2: uart@a,3 {
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compatible = "pci8086,8813.00",
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"pci8086,8813",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025300 0x0 0x0 0x0 0x0
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0x01025310 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart3: uart@a,4 {
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compatible = "pci8086,8814.00",
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"pci8086,8814",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025400 0x0 0x0 0x0 0x0
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0x01025410 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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};
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};
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irq-router@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,irq-router";
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intel,pirq-config = "pci";
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0xdee0>;
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intel,pirq-routing = <
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/* TunnelCreek PCI devices */
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PCI_BDF(0, 2, 0) INTA PIRQE
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PCI_BDF(0, 3, 0) INTA PIRQF
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PCI_BDF(0, 23, 0) INTA PIRQA
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PCI_BDF(0, 23, 0) INTB PIRQB
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PCI_BDF(0, 23, 0) INTC PIRQC
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PCI_BDF(0, 23, 0) INTD PIRQD
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PCI_BDF(0, 24, 0) INTA PIRQB
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PCI_BDF(0, 24, 0) INTB PIRQC
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PCI_BDF(0, 24, 0) INTC PIRQD
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PCI_BDF(0, 24, 0) INTD PIRQA
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PCI_BDF(0, 25, 0) INTA PIRQC
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PCI_BDF(0, 25, 0) INTB PIRQD
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PCI_BDF(0, 25, 0) INTC PIRQA
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PCI_BDF(0, 25, 0) INTD PIRQB
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PCI_BDF(0, 26, 0) INTA PIRQD
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PCI_BDF(0, 26, 0) INTB PIRQA
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PCI_BDF(0, 26, 0) INTC PIRQB
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PCI_BDF(0, 26, 0) INTD PIRQC
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PCI_BDF(0, 27, 0) INTA PIRQG
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/*
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* Topcliff PCI devices
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*
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* Note on the Crown Bay board, Topcliff chipset
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* is connected to TunnelCreek PCIe port 0, so
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* its bus number is 1 for its PCIe port and 2
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* for its PCI devices per U-Boot current PCI
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* bus enumeration algorithm.
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*/
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(2, 0, 1) INTA PIRQA
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PCI_BDF(2, 0, 2) INTA PIRQA
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PCI_BDF(2, 2, 0) INTB PIRQD
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PCI_BDF(2, 2, 1) INTB PIRQD
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PCI_BDF(2, 2, 2) INTB PIRQD
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PCI_BDF(2, 2, 3) INTB PIRQD
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PCI_BDF(2, 2, 4) INTB PIRQD
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PCI_BDF(2, 4, 0) INTC PIRQC
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PCI_BDF(2, 4, 1) INTC PIRQC
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PCI_BDF(2, 6, 0) INTD PIRQB
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PCI_BDF(2, 8, 0) INTA PIRQA
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PCI_BDF(2, 8, 1) INTA PIRQA
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PCI_BDF(2, 8, 2) INTA PIRQA
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PCI_BDF(2, 8, 3) INTA PIRQA
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PCI_BDF(2, 10, 0) INTB PIRQD
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PCI_BDF(2, 10, 1) INTB PIRQD
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PCI_BDF(2, 10, 2) INTB PIRQD
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PCI_BDF(2, 10, 3) INTB PIRQD
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PCI_BDF(2, 10, 4) INTB PIRQD
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PCI_BDF(2, 12, 0) INTC PIRQC
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PCI_BDF(2, 12, 1) INTC PIRQC
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PCI_BDF(2, 12, 2) INTC PIRQC
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PCI_BDF(2, 12, 3) INTC PIRQC
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PCI_BDF(2, 12, 4) INTC PIRQC
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>;
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};
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};
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};
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