mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 22:03:44 +09:00
9721027aae
Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini <trini@ti.com>
179 lines
3.2 KiB
C
179 lines
3.2 KiB
C
/*
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* sys_info.c
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*
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* System information functions
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <power/tps65910.h>
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struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
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/**
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* get_cpu_rev(void) - extract rev info
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*/
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u32 get_cpu_rev(void)
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{
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u32 id;
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u32 rev;
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id = readl(DEVICE_ID);
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rev = (id >> 28) & 0xff;
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return rev;
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}
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/**
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* get_cpu_type(void) - extract cpu info
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*/
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u32 get_cpu_type(void)
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{
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u32 id = 0;
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u32 partnum;
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id = readl(DEVICE_ID);
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partnum = (id >> 12) & 0xffff;
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return partnum;
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}
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/**
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* get_board_rev() - setup to pass kernel board revision information
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* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
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*/
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u32 get_board_rev(void)
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{
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return BOARD_REV_ID;
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}
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/**
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* get_device_type(): tell if GP/HS/EMU/TST
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*/
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u32 get_device_type(void)
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{
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int mode;
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mode = readl(&cstat->statusreg) & (DEVICE_MASK);
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return mode >>= 8;
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}
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/**
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* get_sysboot_value(void) - return SYS_BOOT[4:0]
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*/
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u32 get_sysboot_value(void)
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{
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int mode;
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mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
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return mode;
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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/**
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* Print CPU information
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*/
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int print_cpuinfo(void)
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{
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char *cpu_s, *sec_s;
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switch (get_cpu_type()) {
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case AM335X:
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cpu_s = "AM335X";
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break;
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case TI81XX:
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cpu_s = "TI81XX";
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break;
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default:
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cpu_s = "Unknown cpu type";
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break;
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}
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switch (get_device_type()) {
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case TST_DEVICE:
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sec_s = "TST";
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break;
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case EMU_DEVICE:
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sec_s = "EMU";
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break;
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case HS_DEVICE:
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sec_s = "HS";
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break;
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case GP_DEVICE:
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sec_s = "GP";
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break;
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default:
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sec_s = "?";
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}
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printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#ifdef CONFIG_AM33XX
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int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
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{
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int sil_rev;
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sil_rev = readl(&cdev->deviceid) >> 28;
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if (sil_rev == 1)
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/* PG 2.0, efuse may not be set. */
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return MPUPLL_M_800;
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else if (sil_rev >= 2) {
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/* Check what the efuse says our max speed is. */
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int efuse_arm_mpu_max_freq;
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efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
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switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
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case AM335X_ZCZ_1000:
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return MPUPLL_M_1000;
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case AM335X_ZCZ_800:
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return MPUPLL_M_800;
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case AM335X_ZCZ_720:
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return MPUPLL_M_720;
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case AM335X_ZCZ_600:
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case AM335X_ZCE_600:
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return MPUPLL_M_600;
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case AM335X_ZCZ_300:
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case AM335X_ZCE_300:
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return MPUPLL_M_300;
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}
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}
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/* PG 1.0 or otherwise unknown, use the PG1.0 max */
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return MPUPLL_M_720;
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}
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int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
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{
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/* For PG2.1 and later, we have one set of values. */
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if (sil_rev >= 2) {
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switch (frequency) {
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case MPUPLL_M_1000:
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return TPS65910_OP_REG_SEL_1_3_2_5;
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case MPUPLL_M_800:
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return TPS65910_OP_REG_SEL_1_2_6;
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case MPUPLL_M_720:
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return TPS65910_OP_REG_SEL_1_2_0;
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case MPUPLL_M_600:
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case MPUPLL_M_300:
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return TPS65910_OP_REG_SEL_1_1_3;
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}
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}
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/* Default to PG1.0/PG2.0 values. */
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return TPS65910_OP_REG_SEL_1_1_3;
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}
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#endif
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