mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
443 lines
12 KiB
C
443 lines
12 KiB
C
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2006
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* Eric Schumann, Phytec Messatechnik GmbH
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*
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* (C) Copyright 2009
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* Jon Smirl <jonsmirl@gmail.com>
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*
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* (C) Copyright 2009
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* Eric Millbrandt, DEKA Research and Development Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_BOARDINFO "galaxy5200"
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
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/* define gps port conf. */
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/* register later on to */
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/* enable UART function! */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_FAT
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#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
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#if (TEXT_BASE == 0xFE000000) /* Boot low */
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#define CONFIG_SYS_LOWBOOT 1
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#endif
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/* RAMBOOT will be defined automatically in memory section */
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
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#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
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"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
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/* even with bootdelay=0 */
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#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_PREBOOT "echo;" \
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"echo Welcome to U-Boot;"\
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"echo"
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#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
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"bootm ff040000 ff900000 fffc0000"
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#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
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#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#define CONFIG_SYS_XLB_PIPELINING 1
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
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/*
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* EEPROM CAT24WC32 configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
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#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_SIZE 4096
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_DS3231 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfe000000
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/*
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* The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
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* variable defined
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*/
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#define CONFIG_SYS_FLASH_SIZE 0x02000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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/* (= chip selects) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/*
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* Use hardware protection. This seems required, as the BDI uses hardware
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* protection. Without this, U-Boot can't work with this sectors as its
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* protection is software only by default.
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*/
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#define CONFIG_SYS_FLASH_PROTECTION 1
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
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/* beginning of the EEPROM */
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#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* SDRAM configuration
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*/
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#define SDRAM_DDR 1
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x71500F00
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#define SDRAM_CONFIG1 0x73711930
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#define SDRAM_CONFIG2 0x47770000
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
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/* bootloader or debugger config */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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/* End of used area in SPRAM */
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#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
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/* Size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
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CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* Chip Select configuration for NAND flash */
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#define CONFIG_SYS_CS1_START 0x20000000
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#define CONFIG_SYS_CS1_SIZE 0x90000
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#define CONFIG_SYS_CS1_CFG 0x00025b00
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/* Chip Select configuration for Epson S1D13513 */
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#define CONFIG_SYS_CS3_START 0x10000000
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#define CONFIG_SYS_CS3_SIZE 0x400000
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#define CONFIG_SYS_CS3_CFG 0xffff3d10
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x01
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#define CONFIG_NO_AUTOLOAD 1
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/*
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* GPIO configuration
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*
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* GPS port configuration
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*
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* [29:31] = 01x
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* AC97 on PSC1
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* PSC1_0 -> AC97 SDATA out
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* PSC1_1 -> AC97 SDTA in
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* PSC1_2 -> AC97 SYNC out
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* PSC1_3 -> AC97 bitclock out
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* PSC1_4 -> AC97 reset out
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*
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* [28] = Reserved
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*
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* [25:27] = 110
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* SPI on PSC2
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* PSC2_0 -> MOSI
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* PSC2_1 -> MISO
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* PSC2_2 -> n/a
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* PSC2_3 -> CLK
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* PSC2_4 -> SS
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*
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* [24] = Reserved
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*
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* [20:23] = 0001
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* USB on PSC3
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* PSC3_0 -> USB_OE OE out
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* PSC3_1 -> USB_TXN Tx- out
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* PSC3_2 -> USB_TXP Tx+ out
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* PSC3_3 -> USB_TXD
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* PSC3_4 -> USB_RXP Rx+ in
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* PSC3_5 -> USB_RXN Rx- in
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* PSC3_6 -> USB_PWR PortPower out
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* PSC3_7 -> USB_SPEED speed out
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* PSC3_8 -> USB_SUSPEND suspend
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* PSC3_9 -> USB_OVRCURNT overcurrent in
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*
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* [18:19] = 10
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* Two UARTs
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*
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* [17] = 0
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* USB differential mode
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*
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* [16] = 1
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* PCI disabled
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*
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* [12:15] = 0101
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* Ethernet 100Mbit with MD
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* ETH_0 -> ETH Txen
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* ETH_1 -> ETH TxD0
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* ETH_2 -> ETH TxD1
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* ETH_3 -> ETH TxD2
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* ETH_4 -> ETH TxD3
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* ETH_5 -> ETH Txerr
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* ETH_6 -> ETH MDC
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* ETH_7 -> ETH MDIO
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* ETH_8 -> ETH RxDv
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* ETH_9 -> ETH RxCLK
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* ETH_10 -> ETH Collision
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* ETH_11 -> ETH TxD
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* ETH_12 -> ETH RxD0
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* ETH_13 -> ETH RxD1
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* ETH_14 -> ETH RxD2
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* ETH_15 -> ETH RxD3
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* ETH_16 -> ETH Rxerr
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* ETH_17 -> ETH CRS
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*
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* [9:11] = 111
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* SPI on PSC6
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* PSC6_0 -> MISO
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* PSC6_1 -> SS#
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* PSC6_2 -> MOSI
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* PSC6_3 -> CLK
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*
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* [8] = 0
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* IrDA/USB 48MHz clock generated internally
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*
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* [6:7] = 01
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* ATA chip selects on csb_4/5
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* CSB_4 -> ATA_CS0 out
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* CSB_5 -> ATA_CS1 out
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*
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* [5] = 1
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* PSC3_4 is used as CS6
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*
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* [4] = 1
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* PSC3_5 is used as CS7
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*
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* [2:3] = 00
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* No Alternatives
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*
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* [1] = 0
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* gpio_wkup_7 is GPIO
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*
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* [0] = 0
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* gpio_wkup_6 is GPIO
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*
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CRC32_VERIFY 1
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_DNS | \
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CONFIG_BOOTP_DNS2 | \
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CONFIG_BOOTP_SEND_HOSTNAME )
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#define CONFIG_VERSION_VARIABLE 1
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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/* no burst access on the LPB */
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#define CONFIG_SYS_CS_BURST 0x00000000
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/* one deadcycle for the 33MHz statemachine */
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
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#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*
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* USB settings
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*/
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#define CONFIG_USB_CLOCK 0x0001bbbb
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/* USB is on PSC3 */
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#define CONFIG_PSC3_USB
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#define CONFIG_USB_CONFIG 0x00000100
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/*
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* IDE/ATA stuff Supports IDE harddisk
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#define CONFIG_ATAPI 1
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/* we enable IDE and FAT support, so we also need partition support */
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#define CONFIG_DOS_PARTITION 1
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/*
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* Open Firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_CPU "PowerPC,5200@0"
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#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
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#define OF_SOC "soc5200@f0000000"
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
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#endif /* __CONFIG_H */
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