mirror of
https://github.com/brain-hackers/u-boot-brain
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1f1a02123c
This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock. This uses the RFC clock bindings from Grant Likely so may change later: https://lkml.org/lkml/2011/12/12/498 It is taken from Stephen Warren's patch here: http://patchwork.ozlabs.org/patch/141359/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
185 lines
3.6 KiB
Plaintext
185 lines
3.6 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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intc: interrupt-controller@50041000 {
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compatible = "nvidia,tegra20-gic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 70 >;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 116 >;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 124 >;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000D000 0x200>;
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interrupts = < 85 >;
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};
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i2s@70002800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = < 45 >;
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dma-channel = < 2 >;
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};
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i2s@70002a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = < 35 >;
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dma-channel = < 1 >;
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};
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das@70000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 64 65 66 67 87 119 121 >;
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#gpio-cells = <2>;
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gpio-controller;
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};
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pinmux: pinmux@70000000 {
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compatible = "nvidia,tegra20-pinmux";
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reg = < 0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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0x700000a0 0x14 /* Pull-up/down registers */
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0x70000868 0xa8 >; /* Pad control registers */
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};
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serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 68 >;
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};
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serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 69 >;
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};
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serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 78 >;
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};
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serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = < 122 >;
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};
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serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = < 123 >;
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = < 46 >;
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = < 47 >;
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};
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sdhci@c8000400 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000400 0x200>;
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interrupts = < 51 >;
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};
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sdhci@c8000600 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000600 0x200>;
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interrupts = < 63 >;
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};
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usb@c5000000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5000000 0x4000>;
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interrupts = < 52 >;
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phy_type = "utmi";
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};
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usb@c5004000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5004000 0x4000>;
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interrupts = < 53 >;
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phy_type = "ulpi";
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};
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usb@c5008000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5008000 0x4000>;
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interrupts = < 129 >;
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phy_type = "utmi";
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};
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};
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