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![Horatiu Vultur](/assets/img/avatar_default.png)
The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
514 lines
13 KiB
C
514 lines
13 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <dm/of_addr.h>
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#include <fdt_support.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <miiphy.h>
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#include <net.h>
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#include <wait_bit.h>
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#include "mscc_miim.h"
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#include "mscc_xfer.h"
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#include "mscc_mac_table.h"
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#define PHY_CFG 0x0
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#define PHY_CFG_ENA 0xF
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#define PHY_CFG_COMMON_RST BIT(4)
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#define PHY_CFG_RST (0xF << 5)
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#define PHY_STAT 0x4
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#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
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#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
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#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
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#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
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#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
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#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
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#define ANA_PGID(x) (0x8c00 + 4 * (x))
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#define SYS_FRM_AGING 0x574
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#define SYS_FRM_AGING_ENA BIT(20)
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#define SYS_SYSTEM_RST_CFG 0x508
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#define SYS_SYSTEM_RST_MEM_INIT BIT(0)
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#define SYS_SYSTEM_RST_MEM_ENA BIT(1)
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#define SYS_SYSTEM_RST_CORE_ENA BIT(2)
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#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x))
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#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3)
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#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
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#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1)
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#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
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#define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x))
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#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
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#define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x))
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#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
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#define QSYS_QMAP 0x112d8
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#define QSYS_EGR_NO_SHARING 0x1129c
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/* Port registers */
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#define DEV_CLOCK_CFG 0x0
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#define DEV_CLOCK_CFG_LINK_SPEED_1000 1
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#define DEV_MAC_ENA_CFG 0x1c
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#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
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#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
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#define DEV_MAC_IFG_CFG 0x30
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#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
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#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
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#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
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#define PCS1G_CFG 0x48
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#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
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#define PCS1G_MODE_CFG 0x4c
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#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
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#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
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#define PCS1G_SD_CFG 0x50
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#define PCS1G_ANEG_CFG 0x54
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#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
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#define QS_XTR_GRP_CFG(x) (4 * (x))
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#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
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#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
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#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
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#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
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#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
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#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
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#define IFH_INJ_BYPASS BIT(31)
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#define IFH_TAG_TYPE_C 0
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#define MAC_VID 1
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#define CPU_PORT 11
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#define INTERNAL_PORT_MSK 0xF
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#define IFH_LEN 4
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#define ETH_ALEN 6
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#define PGID_BROADCAST 13
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#define PGID_UNICAST 14
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#define PGID_SRC 80
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enum ocelot_target {
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ANA,
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QS,
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QSYS,
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REW,
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SYS,
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HSIO,
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PORT0,
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PORT1,
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PORT2,
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PORT3,
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TARGET_MAX,
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};
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#define MAX_PORT (PORT3 - PORT0)
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enum ocelot_mdio_target {
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MIIM,
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PHY,
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TARGET_MDIO_MAX,
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};
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enum ocelot_phy_id {
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INTERNAL,
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EXTERNAL,
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NUM_PHY,
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};
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struct ocelot_private {
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void __iomem *regs[TARGET_MAX];
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struct mii_dev *bus[NUM_PHY];
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};
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static const unsigned long ocelot_regs_qs[] = {
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[MSCC_QS_XTR_RD] = 0x8,
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[MSCC_QS_XTR_FLUSH] = 0x18,
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[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
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[MSCC_QS_INJ_WR] = 0x2c,
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[MSCC_QS_INJ_CTRL] = 0x34,
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};
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static const unsigned long ocelot_regs_ana_table[] = {
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[MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
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[MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
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[MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
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};
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static struct mscc_miim_dev miim[NUM_PHY];
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static void mscc_phy_reset(void)
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{
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writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
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writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
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| PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
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if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
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PHY_STAT_SUPERVISOR_COMPLETE,
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true, 2000, false)) {
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pr_err("Timeout in phy reset\n");
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}
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}
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/* For now only setup the internal mdio bus */
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static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
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{
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unsigned long phy_size[TARGET_MAX];
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phys_addr_t phy_base[TARGET_MAX];
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struct ofnode_phandle_args phandle;
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ofnode eth_node, node, mdio_node;
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struct resource res;
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struct mii_dev *bus;
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fdt32_t faddr;
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int i;
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bus = mdio_alloc();
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if (!bus)
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return NULL;
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/* gathered only the first mdio bus */
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eth_node = dev_read_first_subnode(dev);
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node = ofnode_first_subnode(eth_node);
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ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
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&phandle);
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mdio_node = ofnode_get_parent(phandle.node);
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for (i = 0; i < TARGET_MDIO_MAX; i++) {
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if (ofnode_read_resource(mdio_node, i, &res)) {
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pr_err("%s: get OF resource failed\n", __func__);
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return NULL;
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}
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faddr = cpu_to_fdt32(res.start);
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phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
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phy_size[i] = res.end - res.start;
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}
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strcpy(bus->name, "miim-internal");
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miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
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miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
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bus->priv = &miim[INTERNAL];
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bus->read = mscc_miim_read;
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bus->write = mscc_miim_write;
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if (mdio_register(bus))
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return NULL;
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else
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return bus;
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}
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__weak void mscc_switch_reset(void)
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{
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}
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static void ocelot_stop(struct udevice *dev)
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{
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mscc_switch_reset();
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mscc_phy_reset();
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}
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static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
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{
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int i;
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/* map the 8 CPU extraction queues to CPU port 11 */
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writel(0, priv->regs[QSYS] + QSYS_QMAP);
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for (i = 0; i <= 1; i++) {
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/*
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* Do byte-swap and expect status after last data word
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* Extraction: Mode: manual extraction) | Byte_swap
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*/
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writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
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priv->regs[QS] + QS_XTR_GRP_CFG(i));
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/*
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* Injection: Mode: manual extraction | Byte_swap
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*/
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writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
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priv->regs[QS] + QS_INJ_GRP_CFG(i));
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}
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for (i = 0; i <= 1; i++)
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/* Enable IFH insertion/parsing on CPU ports */
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writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
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SYS_PORT_MODE_INCL_XTR_HDR(1),
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priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
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/*
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* Setup the CPU port as VLAN aware to support switching frames
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* based on tags
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*/
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writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
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MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
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/* Disable learning (only RECV_ENA must be set) */
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writel(ANA_PORT_PORT_CFG_RECV_ENA,
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priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
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/* Enable switching to/from cpu port */
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setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
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QSYS_SWITCH_PORT_MODE_PORT_ENA);
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/* No pause on CPU port - not needed (off by default) */
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clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
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SYS_PAUSE_CFG_PAUSE_ENA);
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setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
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}
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static void ocelot_port_init(struct ocelot_private *priv, int port)
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{
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void __iomem *regs = priv->regs[port];
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/* Enable PCS */
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writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
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/* Disable Signal Detect */
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writel(0, regs + PCS1G_SD_CFG);
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/* Enable MAC RX and TX */
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writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
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regs + DEV_MAC_ENA_CFG);
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/* Clear sgmii_mode_ena */
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writel(0, regs + PCS1G_MODE_CFG);
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/*
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* Clear sw_resolve_ena(bit 0) and set adv_ability to
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* something meaningful just in case
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*/
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writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
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/* Set MAC IFG Gaps */
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writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
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DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
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/* Set link speed and release all resets */
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writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
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/* Make VLAN aware for CPU traffic */
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writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
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MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
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/* Enable the port in the core */
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setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
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QSYS_SWITCH_PORT_MODE_PORT_ENA);
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}
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static int ocelot_switch_init(struct ocelot_private *priv)
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{
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/* Reset switch & memories */
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writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
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priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
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/* Wait to complete */
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if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
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SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
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pr_err("Timeout in memory reset\n");
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return -EIO;
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}
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/* Enable switch core */
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setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
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SYS_SYSTEM_RST_CORE_ENA);
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return 0;
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}
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static int ocelot_initialize(struct ocelot_private *priv)
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{
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int ret, i;
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/* Initialize switch memories, enable core */
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ret = ocelot_switch_init(priv);
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if (ret)
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return ret;
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/*
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* Disable port-to-port by switching
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* Put fron ports in "port isolation modes" - i.e. they cant send
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* to other ports - via the PGID sorce masks.
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*/
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for (i = 0; i <= MAX_PORT; i++)
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writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
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/* Flush queues */
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mscc_flush(priv->regs[QS], ocelot_regs_qs);
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/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
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writel(SYS_FRM_AGING_ENA | (20000000 / 65),
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priv->regs[SYS] + SYS_FRM_AGING);
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for (i = PORT0; i <= PORT3; i++)
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ocelot_port_init(priv, i);
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ocelot_cpu_capture_setup(priv);
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debug("Ports enabled\n");
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return 0;
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}
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static int ocelot_write_hwaddr(struct udevice *dev)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
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pdata->enetaddr, PGID_UNICAST);
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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return 0;
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}
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static int ocelot_start(struct udevice *dev)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff };
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int ret;
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ret = ocelot_initialize(priv);
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if (ret)
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return ret;
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/* Set MAC address tables entries for CPU redirection */
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
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PGID_BROADCAST);
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writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
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priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
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/* It should be setup latter in ocelot_write_hwaddr */
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
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pdata->enetaddr, PGID_UNICAST);
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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return 0;
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}
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static int ocelot_send(struct udevice *dev, void *packet, int length)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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u32 ifh[IFH_LEN];
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int port = BIT(0); /* use port 0 */
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u32 *buf = packet;
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/*
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* Generate the IFH for frame injection
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*
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* The IFH is a 128bit-value
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* bit 127: bypass the analyzer processing
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* bit 56-67: destination mask
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* bit 28-29: pop_cnt: 3 disables all rewriting of the frame
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* bit 20-27: cpu extraction queue mask
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* bit 16: tag type 0: C-tag, 1: S-tag
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* bit 0-11: VID
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*/
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ifh[0] = IFH_INJ_BYPASS;
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ifh[1] = (0xf00 & port) >> 8;
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ifh[2] = (0xff & port) << 24;
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ifh[3] = (IFH_TAG_TYPE_C << 16);
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return mscc_send(priv->regs[QS], ocelot_regs_qs,
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ifh, IFH_LEN, buf, length);
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}
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static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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u32 *rxbuf = (u32 *)net_rx_packets[0];
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int byte_cnt;
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byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
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false);
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*packetp = net_rx_packets[0];
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return byte_cnt;
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}
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static int ocelot_probe(struct udevice *dev)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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int ret, i;
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struct {
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enum ocelot_target id;
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char *name;
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} reg[] = {
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{ SYS, "sys" },
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{ REW, "rew" },
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{ QSYS, "qsys" },
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{ ANA, "ana" },
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{ QS, "qs" },
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{ HSIO, "hsio" },
|
|
{ PORT0, "port0" },
|
|
{ PORT1, "port1" },
|
|
{ PORT2, "port2" },
|
|
{ PORT3, "port3" },
|
|
};
|
|
|
|
for (i = 0; i < ARRAY_SIZE(reg); i++) {
|
|
priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
|
|
if (!priv->regs[reg[i].id]) {
|
|
pr_err
|
|
("Error %d: can't get regs base addresses for %s\n",
|
|
ret, reg[i].name);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
|
|
mscc_phy_reset();
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
phy_connect(priv->bus[INTERNAL], i, dev,
|
|
PHY_INTERFACE_MODE_NONE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ocelot_remove(struct udevice *dev)
|
|
{
|
|
struct ocelot_private *priv = dev_get_priv(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_PHY; i++) {
|
|
mdio_unregister(priv->bus[i]);
|
|
mdio_free(priv->bus[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops ocelot_ops = {
|
|
.start = ocelot_start,
|
|
.stop = ocelot_stop,
|
|
.send = ocelot_send,
|
|
.recv = ocelot_recv,
|
|
.write_hwaddr = ocelot_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id mscc_ocelot_ids[] = {
|
|
{.compatible = "mscc,vsc7514-switch"},
|
|
{ /* Sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ocelot) = {
|
|
.name = "ocelot-switch",
|
|
.id = UCLASS_ETH,
|
|
.of_match = mscc_ocelot_ids,
|
|
.probe = ocelot_probe,
|
|
.remove = ocelot_remove,
|
|
.ops = &ocelot_ops,
|
|
.priv_auto_alloc_size = sizeof(struct ocelot_private),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|