mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
493 lines
11 KiB
C
493 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007
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* Michael Schwingen, <michael@schwingen.org>
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*
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* based in great part on jedec_probe.c from linux kernel:
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* (C) 2000 Red Hat. GPL'd.
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* Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
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*/
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/* The DEBUG define must be before common to enable debugging */
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/*#define DEBUG*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#include <environment.h>
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#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
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/* AMD */
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#define AM29DL800BB 0x22CB
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#define AM29DL800BT 0x224A
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#define AM29F400BB 0x22AB
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#define AM29F800BB 0x2258
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#define AM29F800BT 0x22D6
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#define AM29LV400BB 0x22BA
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#define AM29LV400BT 0x22B9
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#define AM29LV800BB 0x225B
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#define AM29LV800BT 0x22DA
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#define AM29LV160DT 0x22C4
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#define AM29LV160DB 0x2249
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#define AM29F017D 0x003D
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#define AM29F016D 0x00AD
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#define AM29F080 0x00D5
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#define AM29F040 0x00A4
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#define AM29LV040B 0x004F
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#define AM29F032B 0x0041
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#define AM29F002T 0x00B0
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/* SST */
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#define SST39LF800 0x2781
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#define SST39LF160 0x2782
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#define SST39VF1601 0x234b
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#define SST39LF512 0x00D4
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#define SST39LF010 0x00D5
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#define SST39LF020 0x00D6
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#define SST39LF040 0x00D7
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#define SST39SF010A 0x00B5
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#define SST39SF020A 0x00B6
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/* STM */
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#define STM29F400BB 0x00D6
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/* MXIC */
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#define MX29LV040 0x004F
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/* WINBOND */
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#define W39L040A 0x00D6
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/* AMIC */
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#define A29L040 0x0092
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/* EON */
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#define EN29LV040A 0x004F
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/*
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* Unlock address sets for AMD command sets.
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* Intel command sets use the MTD_UADDR_UNNECESSARY.
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* Each identifier, except MTD_UADDR_UNNECESSARY, and
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* MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
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* MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
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* initialization need not require initializing all of the
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* unlock addresses for all bit widths.
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*/
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enum uaddr {
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MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
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MTD_UADDR_0x0555_0x02AA,
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MTD_UADDR_0x0555_0x0AAA,
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MTD_UADDR_0x5555_0x2AAA,
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MTD_UADDR_0x0AAA_0x0555,
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MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
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MTD_UADDR_UNNECESSARY, /* Does not require any address */
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};
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struct unlock_addr {
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u32 addr1;
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u32 addr2;
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};
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/*
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* I don't like the fact that the first entry in unlock_addrs[]
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* exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
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* should not be used. The problem is that structures with
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* initializers have extra fields initialized to 0. It is _very_
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* desireable to have the unlock address entries for unsupported
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* data widths automatically initialized - that means that
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* MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
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* must go unused.
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*/
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static const struct unlock_addr unlock_addrs[] = {
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[MTD_UADDR_NOT_SUPPORTED] = {
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.addr1 = 0xffff,
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.addr2 = 0xffff
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},
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[MTD_UADDR_0x0555_0x02AA] = {
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.addr1 = 0x0555,
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.addr2 = 0x02aa
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},
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[MTD_UADDR_0x0555_0x0AAA] = {
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.addr1 = 0x0555,
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.addr2 = 0x0aaa
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},
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[MTD_UADDR_0x5555_0x2AAA] = {
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.addr1 = 0x5555,
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.addr2 = 0x2aaa
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},
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[MTD_UADDR_0x0AAA_0x0555] = {
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.addr1 = 0x0AAA,
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.addr2 = 0x0555
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},
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[MTD_UADDR_DONT_CARE] = {
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.addr1 = 0x0000, /* Doesn't matter which address */
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.addr2 = 0x0000 /* is used - must be last entry */
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},
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[MTD_UADDR_UNNECESSARY] = {
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.addr1 = 0x0000,
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.addr2 = 0x0000
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}
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};
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struct amd_flash_info {
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const __u16 mfr_id;
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const __u16 dev_id;
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const char *name;
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const int DevSize;
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const int NumEraseRegions;
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const int CmdSet;
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const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
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const ulong regions[6];
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};
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#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
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#define SIZE_64KiB 16
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#define SIZE_128KiB 17
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#define SIZE_256KiB 18
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#define SIZE_512KiB 19
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#define SIZE_1MiB 20
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#define SIZE_2MiB 21
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#define SIZE_4MiB 22
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#define SIZE_8MiB 23
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static const struct amd_flash_info jedec_table[] = {
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#ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
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{
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.mfr_id = (u16)SST_MANUFACT,
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.dev_id = SST39LF020,
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.name = "SST 39LF020",
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.uaddr = {
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[0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
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},
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.DevSize = SIZE_256KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x01000,64),
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}
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},
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#endif
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#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
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{
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.mfr_id = (u16)AMD_MANUFACT,
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.dev_id = AM29LV040B,
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.name = "AMD AM29LV040B",
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.uaddr = {
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[0] = MTD_UADDR_0x0555_0x02AA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000,8),
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}
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},
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{
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.mfr_id = (u16)SST_MANUFACT,
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.dev_id = SST39LF040,
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.name = "SST 39LF040",
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.uaddr = {
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[0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x01000,128),
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}
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},
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{
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.mfr_id = (u16)STM_MANUFACT,
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.dev_id = STM_ID_M29W040B,
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.name = "ST Micro M29W040B",
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.uaddr = {
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[0] = MTD_UADDR_0x0555_0x02AA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000,8),
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}
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},
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{
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.mfr_id = (u16)MX_MANUFACT,
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.dev_id = MX29LV040,
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.name = "MXIC MX29LV040",
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.uaddr = {
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[0] = MTD_UADDR_0x0555_0x02AA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000, 8),
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}
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},
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{
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.mfr_id = (u16)WINB_MANUFACT,
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.dev_id = W39L040A,
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.name = "WINBOND W39L040A",
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.uaddr = {
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[0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000, 8),
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}
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},
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{
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.mfr_id = (u16)AMIC_MANUFACT,
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.dev_id = A29L040,
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.name = "AMIC A29L040",
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.uaddr = {
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[0] = MTD_UADDR_0x0555_0x02AA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000, 8),
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}
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},
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{
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.mfr_id = (u16)EON_MANUFACT,
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.dev_id = EN29LV040A,
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.name = "EON EN29LV040A",
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.uaddr = {
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[0] = MTD_UADDR_0x0555_0x02AA /* x8 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = P_ID_AMD_STD,
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.NumEraseRegions= 1,
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.regions = {
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ERASEINFO(0x10000, 8),
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}
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},
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#endif
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#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
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{
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.mfr_id = (u16)AMD_MANUFACT,
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.dev_id = AM29F400BB,
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.name = "AMD AM29F400BB",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x04000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x10000, 7),
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}
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},
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{
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.mfr_id = (u16)AMD_MANUFACT,
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.dev_id = AM29LV400BB,
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.name = "AMD AM29LV400BB",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x04000,1),
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ERASEINFO(0x02000,2),
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ERASEINFO(0x08000,1),
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ERASEINFO(0x10000,7),
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}
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},
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{
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.mfr_id = (u16)AMD_MANUFACT,
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.dev_id = AM29LV800BB,
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.name = "AMD AM29LV800BB",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_1MiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x04000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x10000, 15),
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}
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},
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{
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.mfr_id = (u16)AMD_MANUFACT,
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.dev_id = AM29LV800BT,
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.name = "AMD AM29LV800BT",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_1MiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x10000, 15),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x04000, 1),
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}
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},
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{
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.mfr_id = (u16)MX_MANUFACT,
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.dev_id = AM29LV800BT,
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.name = "MXIC MX29LV800BT",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_1MiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x10000, 15),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x04000, 1),
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}
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},
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{
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.mfr_id = (u16)EON_ALT_MANU,
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.dev_id = AM29LV800BT,
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.name = "EON EN29LV800BT",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_1MiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions= 4,
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.regions = {
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ERASEINFO(0x10000, 15),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x04000, 1),
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}
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},
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{
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.mfr_id = (u16)STM_MANUFACT,
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.dev_id = STM29F400BB,
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.name = "ST Micro M29F400BB",
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.uaddr = {
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[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
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},
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.DevSize = SIZE_512KiB,
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.CmdSet = CFI_CMDSET_AMD_LEGACY,
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.NumEraseRegions = 4,
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.regions = {
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ERASEINFO(0x04000, 1),
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ERASEINFO(0x02000, 2),
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ERASEINFO(0x08000, 1),
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ERASEINFO(0x10000, 7),
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}
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},
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#endif
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};
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static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
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{
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int i,j;
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int sect_cnt;
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int size_ratio;
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int total_size;
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enum uaddr uaddr_idx;
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size_ratio = info->portwidth / info->chipwidth;
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debug("Found JEDEC Flash: %s\n", jedec_entry->name);
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info->vendor = jedec_entry->CmdSet;
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/* Todo: do we need device-specific timeouts? */
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info->erase_blk_tout = 30000;
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info->buffer_write_tout = 1000;
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info->write_tout = 100;
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info->name = jedec_entry->name;
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/* copy unlock addresses from device table to CFI info struct. This
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is just here because the addresses are in the table anyway - if
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the flash is not detected due to wrong unlock addresses,
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flash_detect_legacy would have to try all of them before we even
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get here. */
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switch(info->chipwidth) {
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case FLASH_CFI_8BIT:
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uaddr_idx = jedec_entry->uaddr[0];
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break;
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case FLASH_CFI_16BIT:
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uaddr_idx = jedec_entry->uaddr[1];
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break;
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case FLASH_CFI_32BIT:
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uaddr_idx = jedec_entry->uaddr[2];
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break;
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default:
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uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
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break;
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}
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debug("unlock address index %d\n", uaddr_idx);
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info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
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info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
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debug("unlock addresses are 0x%lx/0x%lx\n",
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info->addr_unlock1, info->addr_unlock2);
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sect_cnt = 0;
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total_size = 0;
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for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
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ulong erase_region_size = jedec_entry->regions[i] >> 8;
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ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
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total_size += erase_region_size * erase_region_count;
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debug("erase_region_count = %ld erase_region_size = %ld\n",
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erase_region_count, erase_region_size);
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for (j = 0; j < erase_region_count; j++) {
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if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
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printf("ERROR: too many flash sectors\n");
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break;
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}
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info->start[sect_cnt] = base;
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base += (erase_region_size * size_ratio);
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sect_cnt++;
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}
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}
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info->sector_count = sect_cnt;
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info->size = total_size * size_ratio;
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}
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/*-----------------------------------------------------------------------
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* match jedec ids against table. If a match is found, fill flash_info entry
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*/
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int jedec_flash_match(flash_info_t *info, ulong base)
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{
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int ret = 0;
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int i;
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ulong mask = 0xFFFF;
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|
if (info->chipwidth == 1)
|
|
mask = 0xFF;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
|
|
if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
|
|
(jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
|
|
fill_info(info, &jedec_table[i], base);
|
|
ret = 1;
|
|
break;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|