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![Simon Glass](/assets/img/avatar_default.png)
The -ENODEV error value in spi_nor_read_id() is incorrect since there clearly is a device - it just cannot be supported. Use -ENOMEDIUM instead which has the virtue of being less common. Fix the return value in spi_nor_scan(). Also there are a few printf() statements which should be debug() since they bloat the code with unused strings at present. Fix those while here. Signed-off-by: Simon Glass <sjg@chromium.org>
801 lines
19 KiB
C
801 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
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* influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
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*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*
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* Synced from Linux v4.19
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*/
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#include <common.h>
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#include <log.h>
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/math64.h>
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#include <linux/sizes.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/spi-nor.h>
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#include <spi-mem.h>
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#include <spi.h>
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#include "sf_internal.h"
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/* Define max times to check status register before we give up. */
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/*
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* For everything but full-chip erase; probably could be much smaller, but kept
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* around for safety for now
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*/
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#define HZ CONFIG_SYS_HZ
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#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
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static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
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*op, void *buf)
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{
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if (op->data.dir == SPI_MEM_DATA_IN)
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op->data.buf.in = buf;
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else
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op->data.buf.out = buf;
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return spi_mem_exec_op(nor->spi, op);
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}
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static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(len, NULL, 1));
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int ret;
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ret = spi_nor_read_write_reg(nor, &op, val);
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if (ret < 0)
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dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
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code);
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return ret;
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}
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static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(len, NULL, 1));
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return spi_nor_read_write_reg(nor, &op, buf);
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}
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static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
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u_char *buf)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
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SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
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SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
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SPI_MEM_OP_DATA_IN(len, buf, 1));
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size_t remaining = len;
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int ret;
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/* get transfer protocols. */
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op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
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op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
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op.dummy.buswidth = op.addr.buswidth;
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op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
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/* convert the dummy cycles to the number of bytes */
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op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
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while (remaining) {
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op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
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ret = spi_mem_adjust_op_size(nor->spi, &op);
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if (ret)
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return ret;
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret)
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return ret;
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op.addr.val += op.data.nbytes;
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remaining -= op.data.nbytes;
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op.data.buf.in += op.data.nbytes;
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}
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return len;
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}
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#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
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/*
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* Read configuration register, returning its value in the
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* location. Return the configuration register value.
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* Returns negative if error occurred.
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*/
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static int read_cr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
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if (ret < 0) {
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dev_dbg(nor->dev, "error %d reading CR\n", ret);
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return ret;
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}
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return val;
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}
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#endif
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/*
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* Write status register 1 byte
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* Returns negative if error occurred.
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*/
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static inline int write_sr(struct spi_nor *nor, u8 val)
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{
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nor->cmd_buf[0] = val;
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return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
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}
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/*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static inline int write_enable(struct spi_nor *nor)
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{
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return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
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}
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/*
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* Send write disable instruction to the chip.
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*/
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static inline int write_disable(struct spi_nor *nor)
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{
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return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
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}
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static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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{
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return mtd->priv;
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}
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static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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{
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size_t i;
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for (i = 0; i < size; i++)
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if (table[i][0] == opcode)
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return table[i][1];
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/* No conversion found, keep input op code. */
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return opcode;
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}
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static inline u8 spi_nor_convert_3to4_read(u8 opcode)
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{
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static const u8 spi_nor_3to4_read[][2] = {
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{ SPINOR_OP_READ, SPINOR_OP_READ_4B },
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{ SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
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{ SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
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{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
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ARRAY_SIZE(spi_nor_3to4_read));
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}
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static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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const struct flash_info *info)
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{
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nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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}
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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int enable)
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{
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int status;
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bool need_wren = false;
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u8 cmd;
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_ST:
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case SNOR_MFR_MICRON:
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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if (need_wren)
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write_enable(nor);
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cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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status = spi_nor_write_reg(nor, cmd, NULL, 0);
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if (need_wren)
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write_disable(nor);
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if (!status && !enable &&
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JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
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/*
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* On Winbond W25Q256FV, leaving 4byte mode causes
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* the Extended Address Register to be set to 1, so all
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* 3-byte-address reads come from the second 16M.
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* We must clear the register to enable normal behavior.
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*/
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write_enable(nor);
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nor->cmd_buf[0] = 0;
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spi_nor_write_reg(nor, SPINOR_OP_WREAR,
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nor->cmd_buf, 1);
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write_disable(nor);
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}
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return status;
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default:
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/* Spansion style */
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nor->cmd_buf[0] = enable << 7;
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return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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}
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}
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#if defined(CONFIG_SPI_FLASH_SPANSION) || \
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defined(CONFIG_SPI_FLASH_WINBOND) || \
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defined(CONFIG_SPI_FLASH_MACRONIX)
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/*
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* Read the status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_sr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
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if (ret < 0) {
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pr_debug("error %d reading SR\n", (int)ret);
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return ret;
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}
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return val;
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}
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/*
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* Read the flag status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_fsr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
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if (ret < 0) {
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pr_debug("error %d reading FSR\n", ret);
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return ret;
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}
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return val;
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}
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static int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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if (sr < 0)
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return sr;
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return !(sr & SR_WIP);
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}
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static int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int fsr = read_fsr(nor);
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if (fsr < 0)
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return fsr;
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return fsr & FSR_READY;
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}
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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if (fsr < 0)
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return fsr;
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return sr && fsr;
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}
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/*
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* Service routine to read status register until ready, or timeout occurs.
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* Returns non-zero if error.
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*/
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static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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unsigned long timeout)
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{
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unsigned long timebase;
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int ret;
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timebase = get_timer(0);
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while (get_timer(timebase) < timeout) {
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ret = spi_nor_ready(nor);
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if (ret < 0)
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return ret;
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if (ret)
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return 0;
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}
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dev_err(nor->dev, "flash operation timed out\n");
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return -ETIMEDOUT;
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}
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static int spi_nor_wait_till_ready(struct spi_nor *nor)
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{
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return spi_nor_wait_till_ready_with_timeout(nor,
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DEFAULT_READY_WAIT_JIFFIES);
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}
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#endif /* CONFIG_SPI_FLASH_SPANSION */
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/*
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* Erase an address range on the nor chip. The address range may extend
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* one or more erase sectors. Return an error is there is a problem erasing.
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*/
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static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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{
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return -ENOTSUPP;
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}
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static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
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{
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int tmp;
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u8 id[SPI_NOR_MAX_ID_LEN];
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const struct flash_info *info;
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tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
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if (tmp < 0) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
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return ERR_PTR(tmp);
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}
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info = spi_nor_ids;
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for (; info->sector_size != 0; info++) {
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if (info->id_len) {
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if (!memcmp(info->id, id, info->id_len))
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return info;
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}
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}
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dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
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id[0], id[1], id[2]);
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return ERR_PTR(-EMEDIUMTYPE);
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}
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static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
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size_t *retlen, u_char *buf)
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{
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struct spi_nor *nor = mtd_to_spi_nor(mtd);
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int ret;
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dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
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while (len) {
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loff_t addr = from;
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ret = spi_nor_read_data(nor, addr, len, buf);
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if (ret == 0) {
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/* We shouldn't see 0-length reads */
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ret = -EIO;
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goto read_err;
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}
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if (ret < 0)
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goto read_err;
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*retlen += ret;
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buf += ret;
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from += ret;
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len -= ret;
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}
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ret = 0;
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read_err:
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return ret;
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}
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/*
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* Write an address range to the nor chip. Data must be written in
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* FLASH_PAGESIZE chunks. The address range may be any size provided
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* it is within the physical boundaries.
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*/
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static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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size_t *retlen, const u_char *buf)
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{
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return -ENOTSUPP;
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}
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#ifdef CONFIG_SPI_FLASH_MACRONIX
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/**
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* macronix_quad_enable() - set QE bit in Status Register.
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* @nor: pointer to a 'struct spi_nor'
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*
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* Set the Quad Enable (QE) bit in the Status Register.
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*
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* bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int macronix_quad_enable(struct spi_nor *nor)
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{
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int ret, val;
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val = read_sr(nor);
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if (val < 0)
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return val;
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if (val & SR_QUAD_EN_MX)
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return 0;
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write_enable(nor);
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write_sr(nor, val | SR_QUAD_EN_MX);
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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ret = read_sr(nor);
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if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
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dev_err(nor->dev, "Macronix Quad bit not set\n");
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return -EINVAL;
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
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/*
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* Write status Register and configuration register with 2 bytes
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* The first byte will be written to the status register, while the
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* second byte will be written to the configuration register.
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* Return negative if error occurred.
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*/
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static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
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{
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int ret;
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write_enable(nor);
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ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
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if (ret < 0) {
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dev_dbg(nor->dev,
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"error while writing configuration register\n");
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return -EINVAL;
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}
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ret = spi_nor_wait_till_ready(nor);
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if (ret) {
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dev_dbg(nor->dev,
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"timeout while writing configuration register\n");
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return ret;
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}
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return 0;
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}
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/**
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* spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
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* @nor: pointer to a 'struct spi_nor'
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*
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* Set the Quad Enable (QE) bit in the Configuration Register.
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* This function should be used with QSPI memories supporting the Read
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* Configuration Register (35h) instruction.
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*
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* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
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* memories.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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{
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u8 sr_cr[2];
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int ret;
|
|
|
|
/* Check current Quad Enable bit value. */
|
|
ret = read_cr(nor);
|
|
if (ret < 0) {
|
|
dev_dbg(dev, "error while reading configuration register\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ret & CR_QUAD_EN_SPAN)
|
|
return 0;
|
|
|
|
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
|
|
|
|
/* Keep the current value of the Status Register. */
|
|
ret = read_sr(nor);
|
|
if (ret < 0) {
|
|
dev_dbg(dev, "error while reading status register\n");
|
|
return -EINVAL;
|
|
}
|
|
sr_cr[0] = ret;
|
|
|
|
ret = write_sr_cr(nor, sr_cr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Read back and check it. */
|
|
ret = read_cr(nor);
|
|
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
|
|
dev_dbg(nor->dev, "Spansion Quad bit not set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_SPI_FLASH_SPANSION */
|
|
|
|
struct spi_nor_read_command {
|
|
u8 num_mode_clocks;
|
|
u8 num_wait_states;
|
|
u8 opcode;
|
|
enum spi_nor_protocol proto;
|
|
};
|
|
|
|
enum spi_nor_read_command_index {
|
|
SNOR_CMD_READ,
|
|
SNOR_CMD_READ_FAST,
|
|
|
|
/* Quad SPI */
|
|
SNOR_CMD_READ_1_1_4,
|
|
|
|
SNOR_CMD_READ_MAX
|
|
};
|
|
|
|
struct spi_nor_flash_parameter {
|
|
struct spi_nor_hwcaps hwcaps;
|
|
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
|
|
};
|
|
|
|
static void
|
|
spi_nor_set_read_settings(struct spi_nor_read_command *read,
|
|
u8 num_mode_clocks,
|
|
u8 num_wait_states,
|
|
u8 opcode,
|
|
enum spi_nor_protocol proto)
|
|
{
|
|
read->num_mode_clocks = num_mode_clocks;
|
|
read->num_wait_states = num_wait_states;
|
|
read->opcode = opcode;
|
|
read->proto = proto;
|
|
}
|
|
|
|
static int spi_nor_init_params(struct spi_nor *nor,
|
|
const struct flash_info *info,
|
|
struct spi_nor_flash_parameter *params)
|
|
{
|
|
/* (Fast) Read settings. */
|
|
params->hwcaps.mask = SNOR_HWCAPS_READ;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
|
|
0, 0, SPINOR_OP_READ,
|
|
SNOR_PROTO_1_1_1);
|
|
|
|
if (!(info->flags & SPI_NOR_NO_FR)) {
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
|
|
0, 8, SPINOR_OP_READ_FAST,
|
|
SNOR_PROTO_1_1_1);
|
|
}
|
|
|
|
if (info->flags & SPI_NOR_QUAD_READ) {
|
|
params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
|
|
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
|
|
0, 8, SPINOR_OP_READ_1_1_4,
|
|
SNOR_PROTO_1_1_4);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_select_read(struct spi_nor *nor,
|
|
const struct spi_nor_flash_parameter *params,
|
|
u32 shared_hwcaps)
|
|
{
|
|
int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
|
|
int cmd;
|
|
const struct spi_nor_read_command *read;
|
|
|
|
if (best_match < 0)
|
|
return -EINVAL;
|
|
|
|
if (best_match & SNOR_HWCAPS_READ_1_1_4)
|
|
cmd = SNOR_CMD_READ_1_1_4;
|
|
else if (best_match & SNOR_HWCAPS_READ_FAST)
|
|
cmd = SNOR_CMD_READ_FAST;
|
|
else
|
|
cmd = SNOR_CMD_READ;
|
|
|
|
read = ¶ms->reads[cmd];
|
|
nor->read_opcode = read->opcode;
|
|
nor->read_proto = read->proto;
|
|
|
|
/*
|
|
* In the spi-nor framework, we don't need to make the difference
|
|
* between mode clock cycles and wait state clock cycles.
|
|
* Indeed, the value of the mode clock cycles is used by a QSPI
|
|
* flash memory to know whether it should enter or leave its 0-4-4
|
|
* (Continuous Read / XIP) mode.
|
|
* eXecution In Place is out of the scope of the mtd sub-system.
|
|
* Hence we choose to merge both mode and wait state clock cycles
|
|
* into the so called dummy clock cycles.
|
|
*/
|
|
nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
|
|
const struct spi_nor_flash_parameter *params,
|
|
const struct spi_nor_hwcaps *hwcaps)
|
|
{
|
|
u32 shared_mask;
|
|
int err;
|
|
|
|
/*
|
|
* Keep only the hardware capabilities supported by both the SPI
|
|
* controller and the SPI flash memory.
|
|
*/
|
|
shared_mask = hwcaps->mask & params->hwcaps.mask;
|
|
|
|
/* Select the (Fast) Read command. */
|
|
err = spi_nor_select_read(nor, params, shared_mask);
|
|
if (err) {
|
|
dev_dbg(nor->dev,
|
|
"can't select read settings supported by both the SPI controller and memory.\n");
|
|
return err;
|
|
}
|
|
|
|
/* Enable Quad I/O if needed. */
|
|
if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
|
|
switch (JEDEC_MFR(info)) {
|
|
#ifdef CONFIG_SPI_FLASH_MACRONIX
|
|
case SNOR_MFR_MACRONIX:
|
|
err = macronix_quad_enable(nor);
|
|
break;
|
|
#endif
|
|
case SNOR_MFR_ST:
|
|
case SNOR_MFR_MICRON:
|
|
break;
|
|
|
|
default:
|
|
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
|
|
/* Kept only for backward compatibility purpose. */
|
|
err = spansion_read_cr_quad_enable(nor);
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
if (err) {
|
|
dev_dbg(nor->dev, "quad mode not supported\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_nor_init(struct spi_nor *nor)
|
|
{
|
|
if (nor->addr_width == 4 &&
|
|
(JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
|
|
!(nor->info->flags & SPI_NOR_4B_OPCODES)) {
|
|
/*
|
|
* If the RESET# pin isn't hooked up properly, or the system
|
|
* otherwise doesn't perform a reset command in the boot
|
|
* sequence, it's impossible to 100% protect against unexpected
|
|
* reboots (e.g., crashes). Warn the user (or hopefully, system
|
|
* designer) that this is bad.
|
|
*/
|
|
if (nor->flags & SNOR_F_BROKEN_RESET)
|
|
printf("enabling reset hack; may not recover from unexpected reboots\n");
|
|
set_4byte(nor, nor->info, 1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int spi_nor_scan(struct spi_nor *nor)
|
|
{
|
|
struct spi_nor_flash_parameter params;
|
|
const struct flash_info *info = NULL;
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
struct spi_nor_hwcaps hwcaps = {
|
|
.mask = SNOR_HWCAPS_READ |
|
|
SNOR_HWCAPS_READ_FAST
|
|
};
|
|
struct spi_slave *spi = nor->spi;
|
|
int ret;
|
|
|
|
/* Reset SPI protocol for all commands. */
|
|
nor->reg_proto = SNOR_PROTO_1_1_1;
|
|
nor->read_proto = SNOR_PROTO_1_1_1;
|
|
nor->write_proto = SNOR_PROTO_1_1_1;
|
|
|
|
if (spi->mode & SPI_RX_QUAD)
|
|
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
|
|
|
|
info = spi_nor_read_id(nor);
|
|
if (IS_ERR_OR_NULL(info))
|
|
return PTR_ERR(info);
|
|
/* Parse the Serial Flash Discoverable Parameters table. */
|
|
ret = spi_nor_init_params(nor, info, ¶ms);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mtd->name = "spi-flash";
|
|
mtd->priv = nor;
|
|
mtd->type = MTD_NORFLASH;
|
|
mtd->writesize = 1;
|
|
mtd->flags = MTD_CAP_NORFLASH;
|
|
mtd->size = info->sector_size * info->n_sectors;
|
|
mtd->_erase = spi_nor_erase;
|
|
mtd->_read = spi_nor_read;
|
|
mtd->_write = spi_nor_write;
|
|
|
|
nor->size = mtd->size;
|
|
|
|
if (info->flags & USE_FSR)
|
|
nor->flags |= SNOR_F_USE_FSR;
|
|
if (info->flags & USE_CLSR)
|
|
nor->flags |= SNOR_F_USE_CLSR;
|
|
|
|
if (info->flags & SPI_NOR_NO_FR)
|
|
params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
|
|
|
|
/*
|
|
* Configure the SPI memory:
|
|
* - select op codes for (Fast) Read, Page Program and Sector Erase.
|
|
* - set the number of dummy cycles (mode cycles + wait states).
|
|
* - set the SPI protocols for register and memory accesses.
|
|
* - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
|
|
*/
|
|
ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (nor->addr_width) {
|
|
/* already configured from SFDP */
|
|
} else if (info->addr_width) {
|
|
nor->addr_width = info->addr_width;
|
|
} else if (mtd->size > 0x1000000) {
|
|
/* enable 4-byte addressing if the device exceeds 16MiB */
|
|
nor->addr_width = 4;
|
|
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
|
|
info->flags & SPI_NOR_4B_OPCODES)
|
|
spi_nor_set_4byte_opcodes(nor, info);
|
|
} else {
|
|
nor->addr_width = 3;
|
|
}
|
|
|
|
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
|
|
dev_dbg(dev, "address width is too large: %u\n",
|
|
nor->addr_width);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Send all the required SPI flash commands to initialize device */
|
|
nor->info = info;
|
|
ret = spi_nor_init(nor);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|