Fabio Estevam 29bc24ec4f mx6sxsabresd: Fix Ethernet PHY reset sequence ... Since commit 59370f3fcd ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional. This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. Fix this by calling enable_fec_anatop_clock() earlier and also by adding a 10ms reset delay as recommended in the AR8031 datasheet. Suggested-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>		2015-12-07 14:55:24 +01:00
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imximage.cfg	mx6sxsabresd: Update DDR initialization	2014-08-20 12:41:41 +02:00
Kconfig	mx6: remove SYS_SOC from board Kconfig	2015-09-13 10:37:29 +02:00
MAINTAINERS	imx:mx6sxsabresd board spl support	2015-01-22 09:56:06 +01:00
Makefile	mx6sx: Add initial support for mx6sxsabresd board	2014-07-10 15:29:16 +02:00
mx6sxsabresd.c	mx6sxsabresd: Fix Ethernet PHY reset sequence	2015-12-07 14:55:24 +01:00