mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
193 lines
4.8 KiB
C
193 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Aeronix Zipit Z2 configuration file
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*
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* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
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#undef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_PREBOOT
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_ADDR 0x40000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
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"then " \
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"source 0xa0000000; " \
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"else " \
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"bootm 0x50000; " \
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"fi; "
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#define CONFIG_TIMESTAMP
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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/*
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* Serial Console Configuration
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* STUART - the lower serial port on Colibri board
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*/
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#define CONFIG_STUART 1
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/*
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* Bootloader Components Configuration
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*/
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/*
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* MMC Card Configuration
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#endif
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/*
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* SPI and LCD
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*/
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#ifdef CONFIG_CMD_SPI
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#define CONFIG_SOFT_SPI
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#define CONFIG_LCD_ROTATION
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#define CONFIG_PXA_LCD
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#define CONFIG_LMS283GF05
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#define SPI_DELAY udelay(10)
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#define SPI_SDA(val) zipitz2_spi_sda(val)
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#define SPI_SCL(val) zipitz2_spi_scl(val)
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#define SPI_READ zipitz2_spi_read()
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#ifndef __ASSEMBLY__
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void zipitz2_spi_sda(int);
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void zipitz2_spi_scl(int);
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unsigned char zipitz2_spi_read(void);
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#endif
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#endif
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
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/*
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* SRAM Map
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*/
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#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
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#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
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/*
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* NOR FLASH
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*/
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
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#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
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#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
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#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
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#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
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#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
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#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
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#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000020
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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#define CONFIG_SYS_GPCR3_VAL 0x00000000
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#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
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#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
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#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
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#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
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#define CONFIG_SYS_GPSR0_VAL 0x06080400
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#define CONFIG_SYS_GPSR1_VAL 0x007f0000
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#define CONFIG_SYS_GPSR2_VAL 0x032a0000
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#define CONFIG_SYS_GPSR3_VAL 0x00000180
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#define CONFIG_SYS_PSSR_VAL 0x30
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/*
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* Clock settings
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*/
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#define CONFIG_SYS_CKEN 0x00511220
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#define CONFIG_SYS_CCCR 0x00000190
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
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#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
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#define CONFIG_SYS_MSC2_VAL 0x0000b884
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#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
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#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
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#define CONFIG_SYS_MDMRS_VAL 0x00000000
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#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000001
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#define CONFIG_SYS_MCMEM0_VAL 0x00014307
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#define CONFIG_SYS_MCMEM1_VAL 0x00014307
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#define CONFIG_SYS_MCATT0_VAL 0x0001c787
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#define CONFIG_SYS_MCATT1_VAL 0x0001c787
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#define CONFIG_SYS_MCIO0_VAL 0x0001430f
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#define CONFIG_SYS_MCIO1_VAL 0x0001430f
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#include "pxa-common.h"
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#endif /* __CONFIG_H */
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