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![Simon Glass](/assets/img/avatar_default.png)
Move env_set_ulong() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
191 lines
4.7 KiB
C
191 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for B&R BRPPT1
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*
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* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------------------*/
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/* -- defines for GPIO -- */
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#define REPSWITCH (0+20) /* GPIO0_20 */
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#if defined(CONFIG_SPL_BUILD)
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/* TODO: check ram-timing ! */
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK/1000000)
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static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int rc;
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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/*
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* in TRM they write a reset value of 1 (=CLK_M_OSC) for the
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* CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
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* the source of timer6 clk to CLK_M_OSC
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*/
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writel(0x01, &cmdpll->clktimer6clk);
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/* enable additional clocks of modules which are accessed later */
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u32 *const clk_domains[] = {
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&cmper->lcdcclkstctrl,
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0
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};
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u32 *const clk_modules_tsspecific[] = {
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&cmper->lcdclkctrl,
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&cmper->timer5clkctrl,
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&cmper->timer6clkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
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/* setup I2C */
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enable_i2c_pin_mux();
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pmicsetup(0, 0);
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/* peripheral reset */
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rc = gpio_request(64 + 29, "GPMC_WAIT1");
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if (rc != 0)
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printf("cannot request GPMC_WAIT1 GPIO!\n");
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rc = gpio_direction_output(64 + 29, 1);
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if (rc != 0)
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printf("cannot set GPMC_WAIT1 GPIO!\n");
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rc = gpio_request(64 + 28, "GPMC_WAIT0");
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if (rc != 0)
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printf("cannot request GPMC_WAIT0 GPIO!\n");
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rc = gpio_direction_output(64 + 28, 1);
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if (rc != 0)
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printf("cannot set GPMC_WAIT0 GPIO!\n");
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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/* Basic board specific setup. Pinmux has been handled already. */
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND
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gpmc_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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static char *bootmodeascii[16] = {
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"BOOT", "reserved", "reserved", "reserved",
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"RUN", "reserved", "reserved", "reserved",
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"reserved", "reserved", "reserved", "reserved",
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"PME", "reserved", "reserved", "DIAG",
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};
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int board_late_init(void)
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{
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unsigned char bmode = 0;
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ulong bootcount = 0;
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int rc;
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bootcount = bootcount_load() & 0xF;
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rc = gpio_request(REPSWITCH, "REPSWITCH");
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if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
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bmode = 12;
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else if (bootcount > 0)
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bmode = 0;
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else
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bmode = 4;
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printf("Mode: %s\n", bootmodeascii[bmode & 0x0F]);
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env_set_ulong("b_mode", bmode);
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/* get sure that bootcmd isn't affected by any bootcount value */
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env_set_ulong("bootlimit", 0);
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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