mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
ccdd6eaecb
This call is more of an architecture requirement than a board one, so move it there. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
164 lines
3.6 KiB
C
164 lines
3.6 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/uart.h>
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#include <spi.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* UARTs which we can enable */
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UARTA = 1 << 0,
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UARTB = 1 << 1,
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UARTD = 1 << 3,
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};
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const struct tegra2_sysinfo sysinfo = {
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CONFIG_TEGRA2_BOARD_STRING
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};
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/*
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* Routine: timer_init
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* Description: init the timestamp and lastinc value
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*/
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int timer_init(void)
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{
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return 0;
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}
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static void enable_uart(enum periph_id pid)
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{
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/* Assert UART reset and enable clock */
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reset_set_enable(pid, 1);
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clock_enable(pid);
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clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
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/* wait for 2us */
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udelay(2);
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/* De-assert reset to UART */
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reset_set_enable(pid, 0);
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}
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/*
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* Routine: clock_init_uart
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* Description: init clock for the UART(s)
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*/
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static void clock_init_uart(int uart_ids)
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{
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if (uart_ids & UARTA)
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enable_uart(PERIPH_ID_UART1);
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if (uart_ids & UARTB)
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enable_uart(PERIPH_ID_UART2);
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if (uart_ids & UARTD)
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enable_uart(PERIPH_ID_UART4);
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}
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/*
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* Routine: pin_mux_uart
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* Description: setup the pin muxes/tristate values for the UART(s)
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*/
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static void pin_mux_uart(int uart_ids)
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{
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if (uart_ids & UARTA) {
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pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
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pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
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pinmux_tristate_disable(PINGRP_IRRX);
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pinmux_tristate_disable(PINGRP_IRTX);
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}
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if (uart_ids & UARTB) {
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pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
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pinmux_tristate_disable(PINGRP_UAD);
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}
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if (uart_ids & UARTD) {
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pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
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pinmux_tristate_disable(PINGRP_GMC);
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}
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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/* Do clocks and UART first so that printf() works */
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clock_init();
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clock_verify();
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#ifdef CONFIG_SPI_UART_SWITCH
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gpio_config_uart();
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#endif
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#ifdef CONFIG_TEGRA2_SPI
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spi_init();
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#endif
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int uart_ids = 0; /* bit mask of which UART ids to enable */
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#ifdef CONFIG_TEGRA2_ENABLE_UARTA
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uart_ids |= UARTA;
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#endif
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#ifdef CONFIG_TEGRA2_ENABLE_UARTB
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uart_ids |= UARTB;
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#endif
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#ifdef CONFIG_TEGRA2_ENABLE_UARTD
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uart_ids |= UARTD;
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#endif
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/* Initialize essential common plls */
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clock_early_init();
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/* Initialize UART clocks */
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clock_init_uart(uart_ids);
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/* Initialize periph pinmuxes */
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pin_mux_uart(uart_ids);
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/* Initialize periph GPIOs */
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#ifdef CONFIG_SPI_UART_SWITCH
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gpio_early_init_uart();
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#else
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gpio_config_uart();
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#endif
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return 0;
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}
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#endif /* EARLY_INIT */
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