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This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
27 lines
736 B
Plaintext
27 lines
736 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CLK_ANALOGBITS_WRPLL_CLN28HPC
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bool
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config CLK_SIFIVE
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bool "SiFive SoC driver support"
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depends on CLK
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help
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SoC drivers for SiFive Linux-capable SoCs.
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config CLK_SIFIVE_FU540_PRCI
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bool "PRCI driver for SiFive FU540 SoCs"
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depends on CLK_SIFIVE
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select CLK_ANALOGBITS_WRPLL_CLN28HPC
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help
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Supports the Power Reset Clock interface (PRCI) IP block found in
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FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
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enable this driver.
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config CLK_SIFIVE_GEMGXL_MGMT
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bool "GEMGXL management for SiFive FU540 SoCs"
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depends on CLK_SIFIVE
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help
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Supports the GEMGXL management IP block found in FU540 SoCs to
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control GEM TX clock operation mode for 10/100/1000 Mbps.
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