mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 05:43:21 +09:00
![Alison Wang](/assets/img/avatar_default.png)
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
20 lines
397 B
C
20 lines
397 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2015 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#ifndef __FSL_LS102XA_SOC_H
|
|
#define __FSL_LS102XA_SOC_H
|
|
|
|
unsigned int get_soc_major_rev(void);
|
|
int arch_soc_init(void);
|
|
int ls102xa_smmu_stream_id_init(void);
|
|
|
|
void erratum_a008850_post(void);
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
|
void erratum_a010315(void);
|
|
#endif
|
|
|
|
#endif /* __FSL_LS102XA_SOC_H */
|