mirror of
https://github.com/brain-hackers/u-boot-brain
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9575c7ebc8
Add 8 gpio controllers in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
183 lines
3.6 KiB
Plaintext
183 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
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*/
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#include "skeleton64.dtsi"
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/ {
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compatible = "brcm,bcm6858";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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l2: l2-cache0 {
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compatible = "cache";
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-pre-reloc;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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uart0: serial@ff800640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x0 0xff800640 0x0 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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wdt1: watchdog@ff802780 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x0 0xff802780 0x0 0x14>;
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clocks = <&periph_osc>;
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};
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wdt2: watchdog@ff8027c0 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x0 0xff8027c0 0x0 0x14>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt1>;
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};
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gpio0: gpio-controller@0xff800500 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800500 0x0 0x4>,
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<0x0 0xff800520 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@0xff800504 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800504 0x0 0x4>,
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<0x0 0xff800524 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio-controller@0xff800508 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800508 0x0 0x4>,
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<0x0 0xff800528 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio3: gpio-controller@0xff80050c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff80050c 0x0 0x4>,
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<0x0 0xff80052c 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio4: gpio-controller@0xff800510 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800510 0x0 0x4>,
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<0x0 0xff800530 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio5: gpio-controller@0xff800514 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800514 0x0 0x4>,
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<0x0 0xff800534 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio6: gpio-controller@0xff800518 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff800518 0x0 0x4>,
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<0x0 0xff800538 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio7: gpio-controller@0xff80051c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x0 0xff80051c 0x0 0x4>,
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<0x0 0xff80053c 0x0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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};
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