mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 18:39:43 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
160 lines
4.8 KiB
C
160 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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*
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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#if defined(CONFIG_M5307)
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/*
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* Simple mcf5307 chip select module init.
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*
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* Note: this chip has an issue reported in the device "errata":
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* MCF5307ER Rev 4.2 reports @ section 35:
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* Corrupted Return PC in Exception Stack Frame
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* When processing an autovectored interrupt an error can occur that
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* causes 0xFFFFFFFF to be written as the return PC value in the
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* exception stack frame. The problem is caused by a conflict between
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* an internal autovector access and a chip select mapped to the IACK
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* address space (0xFFFFXXXX).
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* Workaround:
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* Set the C/I bit in the chip select mask register (CSMR) for the
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* chip select that is mapped to 0xFFFFXXXX.
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* This will prevent the chip select from asserting for IACK accesses.
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*/
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#define MCF5307_SP_ERR_FIX(cs_base, mask) \
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do { \
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if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
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0xffff0000) \
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setbits_be32(&mask, CSMR_CI); \
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} while (0)
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void init_csm(void)
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{
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csm_t *csm = (csm_t *)(MMAP_CSM);
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
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defined(CONFIG_SYS_CS0_CTRL))
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out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
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out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
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out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
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#else
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#warning "Chip Select 0 are not initialized/used"
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
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defined(CONFIG_SYS_CS1_CTRL))
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out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
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out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
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out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
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defined(CONFIG_SYS_CS2_CTRL))
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out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
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out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
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out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
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defined(CONFIG_SYS_CS3_CTRL))
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out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
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out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
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out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
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defined(CONFIG_SYS_CS4_CTRL))
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out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
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out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
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out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
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defined(CONFIG_SYS_CS5_CTRL))
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out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
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out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
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out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
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#endif
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#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
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defined(CONFIG_SYS_CS6_CTRL))
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out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
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out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
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out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
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#endif
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#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
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defined(CONFIG_SYS_CS7_CTRL))
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out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
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out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
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out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
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MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
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#endif
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}
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/*
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* Set up the memory map and initialize registers
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*/
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void cpu_init_f(void)
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{
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sim_t *sim = (sim_t *)(MMAP_SIM);
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out_8(&sim->sypcr, 0x00);
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out_8(&sim->swivr, 0x0f);
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out_8(&sim->swsr, 0x00);
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out_8(&sim->mpark, 0x00);
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intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
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/* timer 2 not masked */
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out_be32(&icr->imr, 0xfffffbff);
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out_8(&icr->icr0, 0x00); /* sw watchdog */
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out_8(&icr->icr1, 0x00); /* timer 1 */
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out_8(&icr->icr2, 0x88); /* timer 2 */
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out_8(&icr->icr3, 0x00); /* i2c */
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out_8(&icr->icr4, 0x00); /* uart 0 */
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out_8(&icr->icr5, 0x00); /* uart 1 */
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out_8(&icr->icr6, 0x00); /* dma 0 */
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out_8(&icr->icr7, 0x00); /* dma 1 */
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out_8(&icr->icr8, 0x00); /* dma 2 */
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out_8(&icr->icr9, 0x00); /* dma 3 */
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/* Chipselect Init */
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init_csm();
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/* enable data/instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return 0;
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}
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void uart_port_conf(int port)
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{
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}
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void arch_preboot_os(void)
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{
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/*
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* OS can change interrupt offsets and are about to boot the OS so
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* we need to make sure we disable all async interrupts.
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*/
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intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
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out_8(&icr->icr1, 0x00); /* timer 1 */
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out_8(&icr->icr2, 0x00); /* timer 2 */
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}
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#endif
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