mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 10:38:00 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
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int get_clocks (void)
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{
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#if defined(CONFIG_M5208)
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pll_t *pll = (pll_t *) MMAP_PLL;
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out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
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out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
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#endif
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
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unsigned long pllcr;
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#ifndef CONFIG_SYS_PLL_BYPASS
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#ifdef CONFIG_M5249
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/* Setup the PLL to run at the specified speed */
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#ifdef CONFIG_SYS_FAST_CLK
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
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#else
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5253
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pllcr = CONFIG_SYS_PLLCR;
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#endif /* CONFIG_M5253 */
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
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udelay(0x20); /* Wait for a lock ... */
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#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
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#endif /* CONFIG_M5249 || CONFIG_M5253 */
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#if defined(CONFIG_M5275)
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pll_t *pll = (pll_t *)(MMAP_PLL);
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/* Setup PLL */
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out_be32(&pll->syncr, 0x01080000);
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while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
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;
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out_be32(&pll->syncr, 0x01000000);
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while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
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;
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#endif
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gd->cpu_clk = CONFIG_SYS_CLK;
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#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
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defined(CONFIG_M5271) || defined(CONFIG_M5275)
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gd->bus_clk = gd->cpu_clk / 2;
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#else
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gd->bus_clk = gd->cpu_clk;
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#endif
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
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gd->arch.i2c2_clk = gd->bus_clk;
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#endif
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#endif
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return (0);
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}
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