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![Bin Meng](/assets/img/avatar_default.png)
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
412 lines
8.9 KiB
C
412 lines
8.9 KiB
C
/*
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* U-Boot - serial.c Blackfin Serial Driver
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
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* BuyWays B.V. (www.buyways.nl)
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*
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* Based heavily on:
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* blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
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* Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
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* Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
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* Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
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*
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* Based on code from 68328 version serial driver imlpementation which was:
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* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
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* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
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* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
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* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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/* Anomaly notes:
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* 05000086 - we don't support autobaud
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* 05000099 - we only use DR bit, so losing others is not a problem
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* 05000100 - we don't use the UART_IIR register
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* 05000215 - we poll the uart (no dma/interrupts)
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* 05000225 - no workaround possible, but this shouldnt cause errors ...
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* 05000230 - we tweak the baud rate calculation slightly
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* 05000231 - we always use 1 stop bit
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* 05000309 - we always enable the uart before we modify it in anyway
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* 05000350 - we always enable the uart regardless of boot mode
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* 05000363 - we don't support break signals, so don't generate one
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*/
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#include <common.h>
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#include <post.h>
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#include <watchdog.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include <asm/blackfin.h>
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#include <asm/serial.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_UART_CONSOLE
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#ifdef CONFIG_DEBUG_SERIAL
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static uart_lsr_t cached_lsr[256];
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static uart_lsr_t cached_rbr[256];
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static size_t cache_count;
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/* The LSR is read-to-clear on some parts, so we have to make sure status
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* bits aren't inadvertently lost when doing various tests. This also
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* works around anomaly 05000099 at the same time by keeping a cumulative
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* tally of all the status bits.
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*/
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static uart_lsr_t uart_lsr_save;
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static uart_lsr_t uart_lsr_read(uint32_t uart_base)
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{
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uart_lsr_t lsr = _lsr_read(pUART);
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uart_lsr_save |= (lsr & (OE|PE|FE|BI));
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return lsr | uart_lsr_save;
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}
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/* Just do the clear for everyone since it can't hurt. */
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static void uart_lsr_clear(uint32_t uart_base)
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{
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uart_lsr_save = 0;
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_lsr_write(pUART, -1);
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}
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#else
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/* When debugging is disabled, we only care about the DR bit, so if other
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* bits get set/cleared, we don't really care since we don't read them
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* anyways (and thus anomaly 05000099 is irrelevant).
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*/
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static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
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{
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return _lsr_read(pUART);
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}
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static void uart_lsr_clear(uint32_t uart_base)
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{
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_lsr_write(pUART, -1);
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}
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#endif
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static void uart_putc(uint32_t uart_base, const char c)
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{
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/* send a \r for compatibility */
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if (c == '\n')
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serial_putc('\r');
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WATCHDOG_RESET();
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/* wait for the hardware fifo to clear up */
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while (!(uart_lsr_read(uart_base) & THRE))
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continue;
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/* queue the character for transmission */
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bfin_write(&pUART->thr, c);
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SSYNC();
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WATCHDOG_RESET();
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}
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static int uart_tstc(uint32_t uart_base)
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{
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WATCHDOG_RESET();
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return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
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}
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static int uart_getc(uint32_t uart_base)
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{
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uint16_t uart_rbr_val;
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/* wait for data ! */
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while (!uart_tstc(uart_base))
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continue;
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/* grab the new byte */
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uart_rbr_val = bfin_read(&pUART->rbr);
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#ifdef CONFIG_DEBUG_SERIAL
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/* grab & clear the LSR */
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uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
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cached_lsr[cache_count] = uart_lsr_val;
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cached_rbr[cache_count] = uart_rbr_val;
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cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
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if (uart_lsr_val & (OE|PE|FE|BI)) {
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printf("\n[SERIAL ERROR]\n");
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do {
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--cache_count;
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printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
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cached_rbr[cache_count], cached_lsr[cache_count]);
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} while (cache_count > 0);
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return -1;
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}
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#endif
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uart_lsr_clear(uart_base);
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return uart_rbr_val;
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}
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#if CONFIG_POST & CONFIG_SYS_POST_UART
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# define LOOP(x) x
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#else
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# define LOOP(x)
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#endif
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#if BFIN_UART_HW_VER < 4
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LOOP(
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static void uart_loop(uint32_t uart_base, int state)
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{
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u16 mcr;
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/* Drain the TX fifo first so bytes don't come back */
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while (!(uart_lsr_read(uart_base) & TEMT))
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continue;
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mcr = bfin_read(&pUART->mcr);
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if (state)
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mcr |= LOOP_ENA | MRTS;
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else
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mcr &= ~(LOOP_ENA | MRTS);
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bfin_write(&pUART->mcr, mcr);
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}
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)
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#else
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LOOP(
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static void uart_loop(uint32_t uart_base, int state)
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{
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u32 control;
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/* Drain the TX fifo first so bytes don't come back */
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while (!(uart_lsr_read(uart_base) & TEMT))
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continue;
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control = bfin_read(&pUART->control);
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if (state)
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control |= LOOP_ENA | MRTS;
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else
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control &= ~(LOOP_ENA | MRTS);
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bfin_write(&pUART->control, control);
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}
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)
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#endif
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static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
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{
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#ifdef CONFIG_DEBUG_EARLY_SERIAL
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serial_early_set_baud(uart_base, baud);
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#else
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uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
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- ANOMALY_05000230;
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/* Program the divisor to get the baud rate we want */
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serial_set_divisor(uart_base, divisor);
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#endif
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}
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static void uart_puts(uint32_t uart_base, const char *s)
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{
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while (*s)
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uart_putc(uart_base, *s++);
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}
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#define DECL_BFIN_UART(n) \
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static int uart##n##_init(void) \
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{ \
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const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
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peripheral_request_list(pins, "bfin-uart"); \
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uart_init(MMR_UART(n)); \
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__serial_set_baud(MMR_UART(n), gd->baudrate); \
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uart_lsr_clear(MMR_UART(n)); \
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return 0; \
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} \
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\
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static int uart##n##_uninit(void) \
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{ \
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return serial_early_uninit(MMR_UART(n)); \
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} \
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\
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static void uart##n##_setbrg(void) \
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{ \
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__serial_set_baud(MMR_UART(n), gd->baudrate); \
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} \
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\
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static int uart##n##_getc(void) \
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{ \
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return uart_getc(MMR_UART(n)); \
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} \
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\
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static int uart##n##_tstc(void) \
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{ \
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return uart_tstc(MMR_UART(n)); \
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} \
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\
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static void uart##n##_putc(const char c) \
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{ \
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uart_putc(MMR_UART(n), c); \
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} \
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\
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static void uart##n##_puts(const char *s) \
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{ \
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uart_puts(MMR_UART(n), s); \
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} \
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\
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LOOP( \
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static void uart##n##_loop(int state) \
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{ \
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uart_loop(MMR_UART(n), state); \
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} \
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) \
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\
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struct serial_device bfin_serial##n##_device = { \
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.name = "bfin_uart"#n, \
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.start = uart##n##_init, \
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.stop = uart##n##_uninit, \
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.setbrg = uart##n##_setbrg, \
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.getc = uart##n##_getc, \
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.tstc = uart##n##_tstc, \
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.putc = uart##n##_putc, \
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.puts = uart##n##_puts, \
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LOOP(.loop = uart##n##_loop) \
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};
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#ifdef UART0_RBR
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DECL_BFIN_UART(0)
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#endif
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#ifdef UART1_RBR
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DECL_BFIN_UART(1)
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#endif
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#ifdef UART2_RBR
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DECL_BFIN_UART(2)
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#endif
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#ifdef UART3_RBR
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DECL_BFIN_UART(3)
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#endif
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__weak struct serial_device *default_serial_console(void)
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{
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#if CONFIG_UART_CONSOLE == 0
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return &bfin_serial0_device;
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#elif CONFIG_UART_CONSOLE == 1
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return &bfin_serial1_device;
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#elif CONFIG_UART_CONSOLE == 2
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return &bfin_serial2_device;
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#elif CONFIG_UART_CONSOLE == 3
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return &bfin_serial3_device;
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#endif
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}
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void bfin_serial_initialize(void)
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{
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#ifdef UART0_RBR
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serial_register(&bfin_serial0_device);
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#endif
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#ifdef UART1_RBR
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serial_register(&bfin_serial1_device);
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#endif
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#ifdef UART2_RBR
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serial_register(&bfin_serial2_device);
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#endif
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#ifdef UART3_RBR
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serial_register(&bfin_serial3_device);
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#endif
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}
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#ifdef CONFIG_DEBUG_EARLY_SERIAL
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inline void uart_early_putc(uint32_t uart_base, const char c)
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{
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/* send a \r for compatibility */
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if (c == '\n')
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uart_early_putc(uart_base, '\r');
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/* wait for the hardware fifo to clear up */
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while (!(_lsr_read(pUART) & THRE))
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continue;
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/* queue the character for transmission */
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bfin_write(&pUART->thr, c);
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SSYNC();
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}
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void uart_early_puts(const char *s)
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{
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while (*s)
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uart_early_putc(UART_BASE, *s++);
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}
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/* Symbol for our assembly to call. */
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void _serial_early_set_baud(uint32_t baud)
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{
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serial_early_set_baud(UART_BASE, baud);
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}
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/* Symbol for our assembly to call. */
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void _serial_early_init(void)
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{
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serial_early_init(UART_BASE);
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}
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#endif
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#elif defined(CONFIG_UART_MEM)
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char serial_logbuf[CONFIG_UART_MEM];
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char *serial_logbuf_head = serial_logbuf;
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int serial_mem_init(void)
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{
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serial_logbuf_head = serial_logbuf;
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return 0;
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}
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void serial_mem_setbrg(void)
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{
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}
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int serial_mem_tstc(void)
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{
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return 0;
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}
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int serial_mem_getc(void)
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{
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return 0;
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}
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void serial_mem_putc(const char c)
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{
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*serial_logbuf_head = c;
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if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
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serial_logbuf_head = serial_logbuf;
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}
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void serial_mem_puts(const char *s)
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{
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while (*s)
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serial_putc(*s++);
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}
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struct serial_device bfin_serial_mem_device = {
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.name = "bfin_uart_mem",
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.start = serial_mem_init,
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.setbrg = serial_mem_setbrg,
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.getc = serial_mem_getc,
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.tstc = serial_mem_tstc,
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.putc = serial_mem_putc,
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.puts = serial_mem_puts,
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};
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__weak struct serial_device *default_serial_console(void)
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{
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return &bfin_serial_mem_device;
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}
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void bfin_serial_initialize(void)
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{
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serial_register(&bfin_serial_mem_device);
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}
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#endif /* CONFIG_UART_MEM */
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