mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
c37207d7f5
U-Boot allows for configurable prompt strings using the CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far, the assumption was that any such user defined problts would contain exactly one "%d" format specifier. But some boards did not. To allow for flexible boot prompts without adding too complex code we now allow to specify the whole list of printf() arguments in the user definition. This is powerful, but requires a responsible user who really understands what he is doing, as he needs to know for exanple which variables are available in the respective context. Signed-off-by: Wolfgang Denk <wd@denx.de>
621 lines
20 KiB
C
621 lines
20 KiB
C
/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* External logbuffer support */
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#define CONFIG_LOGBUFFER
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
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#define CONFIG_LWMON 1 /* ...on a LWMON board */
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/* Default Ethernet MAC address */
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#define CONFIG_ETHADDR 00:11:B0:00:00:00
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/* The default Ethernet MAC address can be overwritten just once */
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#ifdef CONFIG_ETHADDR
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#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
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#define CONFIG_LCD 1 /* use LCD controller ... */
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#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
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#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
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#define CONFIG_LCD_INFO 1 /* ... and some board info */
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#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
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#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
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#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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/* pre-boot commands */
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#define CONFIG_PREBOOT "setenv bootdelay 15"
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#undef CONFIG_BOOTARGS
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_WATCHDOG | \
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CFG_POST_RTC | \
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CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_ETHER | \
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CFG_POST_I2C | \
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CFG_POST_SPI | \
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CFG_POST_USB | \
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CFG_POST_SPR | \
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CFG_POST_SYSMON)
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/*
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* Keyboard commands:
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* # = 0x28 = ENTER : enable bootmessages on LCD
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* 2 = 0x3A+0x3C = F1 + F3 : enable update mode
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* 3 = 0x3C+0x3F = F3 + F6 : enable test mode
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*/
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#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
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/* "gatewayip=10.8.211.250\0" \ */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=40080000\0" \
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"ramdisk_addr=40280000\0" \
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"netmask=255.255.192.0\0" \
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"serverip=10.8.2.101\0" \
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"ipaddr=10.8.57.0\0" \
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"magic_keys=#23\0" \
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"key_magic#=28\0" \
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"key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
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"key_magic2=3A+3C\0" \
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"key_cmd2=echo *** Entering Update Mode ***;" \
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"if fatload ide 0:3 10000 update.scr;" \
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"then autoscr 10000;" \
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"else echo *** UPDATE FAILED ***;" \
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"fi\0" \
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"key_magic3=3C+3F\0" \
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"key_cmd3=echo *** Entering Test Mode ***;" \
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"setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
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"panic=1\0" \
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"add_wdt=setenv bootargs $bootargs $wdt_args\0" \
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"add_misc=setenv bootargs $bootargs runmode\0" \
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"flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
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"bootm $kernel_addr\0" \
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"flash_self=run ramargs addip add_wdt addfb add_misc;" \
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"bootm $kernel_addr $ramdisk_addr\0" \
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"net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
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"run nfsargs addip add_wdt addfb;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"load=tftp 100000 /tftpboot/u-boot.bin\0" \
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"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
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"wdt_args=wdt_8xx=off\0" \
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"verify=no"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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#define CFG_WATCHDOG_FREQ (CFG_HZ / 20)
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#undef CONFIG_STATUS_LED /* Status LED disabled */
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CFG_I2C_SLAVE 0xFE
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#ifdef CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* When the watchdog is enabled, output must be fast enough in Linux.
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*/
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#ifdef CONFIG_WATCHDOG
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#define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 }
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#else
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#endif
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/*----------------------------------------------------------------------*/
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#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
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#undef CONFIG_MODEM_SUPPORT_DEBUG
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#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
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#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
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#if 0
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#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
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#define CONFIG_AUTOBOOT_PROMPT \
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"\nEnter password - autoboot in %d sec...\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
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#endif
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/*----------------------------------------------------------------------*/
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFFF00000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE
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#define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
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/* Buffer size.
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We have two flash devices connected in parallel.
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Each device incorporates a Write Buffer of 32 bytes.
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*/
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#define CFG_FLASH_BUFFER_SIZE (2*32)
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/* Put environment in flash which is much faster to boot than using the EEPROM */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
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#define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
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/*-----------------------------------------------------------------------
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* I2C/EEPROM Configuration
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*/
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#define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
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#define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
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#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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#define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
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#define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
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#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
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#define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
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#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
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#ifdef CONFIG_USE_FRAM /* use FRAM */
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#define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#else /* use EEPROM */
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#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
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#endif /* CONFIG_USE_FRAM */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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/* List of I2C addresses to be verified by POST */
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#ifdef CONFIG_USE_FRAM
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#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
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CFG_I2C_SYSMON_ADDR, \
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CFG_I2C_RTC_ADDR, \
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CFG_I2C_POWER_A_ADDR, \
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CFG_I2C_POWER_B_ADDR, \
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CFG_I2C_KEYBD_ADDR, \
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CFG_I2C_PICIO_ADDR, \
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CFG_I2C_EEPROM_ADDR, \
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}
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#else /* Use EEPROM - which show up on 8 consequtive addresses */
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#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
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CFG_I2C_SYSMON_ADDR, \
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CFG_I2C_RTC_ADDR, \
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CFG_I2C_POWER_A_ADDR, \
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CFG_I2C_POWER_B_ADDR, \
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CFG_I2C_KEYBD_ADDR, \
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CFG_I2C_PICIO_ADDR, \
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CFG_I2C_EEPROM_ADDR+0, \
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CFG_I2C_EEPROM_ADDR+1, \
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CFG_I2C_EEPROM_ADDR+2, \
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CFG_I2C_EEPROM_ADDR+3, \
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CFG_I2C_EEPROM_ADDR+4, \
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CFG_I2C_EEPROM_ADDR+5, \
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CFG_I2C_EEPROM_ADDR+6, \
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CFG_I2C_EEPROM_ADDR+7, \
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}
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#endif /* CONFIG_USE_FRAM */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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/* EARB, DBGC and DBPC are initialised by the HCW */
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/* => 0x000000C0 */
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#define CFG_SIUMCR (SIUMCR_GB5E)
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/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit, set PLL multiplication factor !
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*/
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/* 0x00405000 */
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#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
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#define CFG_PLPRCR \
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( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
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/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
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PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
|
|
)
|
|
|
|
#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SCCR - System Clock and reset Control Register 15-27
|
|
*-----------------------------------------------------------------------
|
|
* Set clock output, timebase and RTC source and divider,
|
|
* power management and some other internal clocks
|
|
*/
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#define SCCR_MASK SCCR_EBDF11
|
|
/* 0x01800000 */
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|
#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
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|
SCCR_RTDIV | SCCR_RTSEL | \
|
|
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
|
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
|
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
|
SCCR_DFNH000 | SCCR_DFLCD100 | \
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|
SCCR_DFALCD01)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
/* 0x00C3 => 0x0003 */
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|
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RCCR - RISC Controller Configuration Register 19-4
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CFG_RCCR 0x0000
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RMDS - RISC Microcode Development Support Control Register
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CFG_RMDS 0
|
|
|
|
/*-----------------------------------------------------------------------
|
|
*
|
|
* Interrupt Levels
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PCMCIA stuff
|
|
*-----------------------------------------------------------------------
|
|
*
|
|
*/
|
|
#define CFG_PCMCIA_MEM_ADDR (0x50000000)
|
|
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
|
#define CFG_PCMCIA_DMA_ADDR (0x54000000)
|
|
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
|
#define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
|
|
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
|
#define CFG_PCMCIA_IO_ADDR (0x5C000000)
|
|
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
|
|
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
|
|
|
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
|
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
|
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
|
|
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
|
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
|
|
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
|
|
|
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
|
|
|
/* Offset for data I/O */
|
|
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
|
|
|
/* Offset for normal register accesses */
|
|
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
|
|
|
/* Offset for alternate registers */
|
|
#define CFG_ATA_ALT_OFFSET 0x0100
|
|
|
|
#define CONFIG_SUPPORT_VFAT /* enable VFAT support */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
*
|
|
*-----------------------------------------------------------------------
|
|
*
|
|
*/
|
|
#define CFG_DER 0
|
|
|
|
/*
|
|
* Init Memory Controller:
|
|
*
|
|
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional
|
|
*/
|
|
|
|
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
|
#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
|
|
|
|
/* used to re-map FLASH:
|
|
* restrict access enough to keep SRAM working (if any)
|
|
* but not too much to meddle with FLASH accesses
|
|
*/
|
|
#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
|
|
#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
|
|
|
|
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
|
|
#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
|
|
|
|
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
|
|
CFG_OR_TIMING_FLASH)
|
|
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
|
|
CFG_OR_TIMING_FLASH)
|
|
/* 16 bit, bank valid */
|
|
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
|
|
|
|
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
|
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
|
|
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
|
|
|
|
/*
|
|
* BR3/OR3: SDRAM
|
|
*
|
|
* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
|
|
*/
|
|
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
|
|
#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
|
|
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
|
|
|
|
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
|
|
|
|
#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
|
|
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
|
|
|
/*
|
|
* BR5/OR5: Touch Panel
|
|
*
|
|
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
|
|
*/
|
|
#define TOUCHPNL_BASE 0x20000000
|
|
#define TOUCHPNL_OR_AM 0xFFFF8000
|
|
#define TOUCHPNL_TIMING OR_SCY_0_CLK
|
|
|
|
#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
|
|
TOUCHPNL_TIMING )
|
|
#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
|
|
|
|
#define CFG_MEMORY_75
|
|
#undef CFG_MEMORY_7E
|
|
#undef CFG_MEMORY_8E
|
|
|
|
/*
|
|
* Memory Periodic Timer Prescaler
|
|
*/
|
|
|
|
/* periodic timer for refresh */
|
|
#define CFG_MPTPR 0x200
|
|
|
|
/*
|
|
* MAMR settings for SDRAM
|
|
*/
|
|
|
|
#define CFG_MAMR_8COL 0x80802114
|
|
#define CFG_MAMR_9COL 0x80904114
|
|
|
|
/*
|
|
* MAR setting for SDRAM
|
|
*/
|
|
#define CFG_MAR 0x00000088
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
#endif /* __CONFIG_H */
|