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![Horatiu Vultur](/assets/img/avatar_default.png)
Update device tree for luton to add support for luton pcb90. This pcb has 24 ports from which 12 ports are connected to SerDes6G. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
253 lines
4.1 KiB
Plaintext
253 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,luton.dtsi"
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#include <dt-bindings/mscc/luton_data.h>
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/ {
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model = "Luton26 PCB090 Reference Board";
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compatible = "mscc,luton-pcb090", "mscc,luton";
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aliases {
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serial0 = &uart0;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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status_green {
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label = "pcb090:green:status";
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gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
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default-state = "on";
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};
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status_red {
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label = "pcb090:red:status";
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gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
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default-state = "off";
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};
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};
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};
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&sgpio {
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status = "okay";
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gpio-ranges = <&sgpio 0 0 96>;
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <0>; /* CS0 */
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spi-cs-high;
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};
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};
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&mdio0 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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};
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phy8: ethernet-phy@8 {
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reg = <8>;
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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};
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phy10: ethernet-phy@10 {
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reg = <10>;
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};
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phy11: ethernet-phy@11 {
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reg = <11>;
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};
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};
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&mdio1 {
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status = "okay";
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phy12: ethernet-phy@12 {
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reg = <0>;
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};
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phy13: ethernet-phy@13 {
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reg = <1>;
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};
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phy14: ethernet-phy@14 {
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reg = <2>;
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};
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phy15: ethernet-phy@15 {
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reg = <3>;
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};
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phy16: ethernet-phy@16 {
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reg = <4>;
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};
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phy17: ethernet-phy@17 {
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reg = <5>;
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};
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phy18: ethernet-phy@18 {
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reg = <6>;
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};
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phy19: ethernet-phy@19 {
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reg = <7>;
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};
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phy20: ethernet-phy@20 {
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reg = <8>;
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};
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phy21: ethernet-phy@21 {
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reg = <9>;
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};
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phy22: ethernet-phy@22 {
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reg = <10>;
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};
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phy23: ethernet-phy@23 {
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reg = <11>;
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};
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};
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&switch {
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ethernet-ports {
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port0: port@0 {
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reg = <0>;
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phy-handle = <&phy0>;
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};
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port1: port@1 {
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reg = <1>;
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phy-handle = <&phy1>;
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};
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port2: port@2 {
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reg = <2>;
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phy-handle = <&phy2>;
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};
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port3: port@3 {
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reg = <3>;
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phy-handle = <&phy3>;
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};
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port4: port@4 {
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reg = <4>;
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phy-handle = <&phy4>;
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};
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port5: port@5 {
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reg = <5>;
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phy-handle = <&phy5>;
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};
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port6: port@6 {
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reg = <6>;
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phy-handle = <&phy6>;
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};
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port7: port@7 {
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reg = <7>;
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phy-handle = <&phy7>;
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};
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port8: port@8 {
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reg = <8>;
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phy-handle = <&phy8>;
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};
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port9: port@9 {
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reg = <9>;
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phy-handle = <&phy9>;
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};
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port10: port@10 {
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reg = <10>;
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phy-handle = <&phy10>;
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};
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port11: port@11 {
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reg = <11>;
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phy-handle = <&phy11>;
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};
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port12: port@12 {
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reg = <12>;
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phy-handle = <&phy12>;
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phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
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};
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port13: port@13 {
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reg = <13>;
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phy-handle = <&phy13>;
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phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
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};
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port14: port@14 {
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reg = <14>;
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phy-handle = <&phy14>;
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phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
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};
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port15: port@15 {
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reg = <15>;
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phy-handle = <&phy15>;
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phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
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};
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port16: port@16 {
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reg = <16>;
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phy-handle = <&phy16>;
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phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
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};
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port17: port@17 {
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reg = <17>;
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phy-handle = <&phy17>;
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phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
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};
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port18: port@18 {
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reg = <18>;
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phy-handle = <&phy18>;
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phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
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};
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port19: port@19 {
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reg = <19>;
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phy-handle = <&phy19>;
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phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
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};
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port20: port@20 {
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reg = <20>;
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phy-handle = <&phy20>;
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phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
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};
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port21: port@21 {
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reg = <21>;
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phy-handle = <&phy21>;
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phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
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};
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port22: port@22 {
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reg = <22>;
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phy-handle = <&phy22>;
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phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
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};
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port23: port@23 {
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reg = <23>;
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phy-handle = <&phy23>;
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phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
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};
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};
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};
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