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https://github.com/brain-hackers/u-boot-brain
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cbe607b920
qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYDUezQAKCRDKSWXLKUoM IbtgAJ9jZ+BOtwFaHR19TENC2DsHTINnnwCfSDn3fU0OFJRI0HD7pRxXr4xrb3M= =Kr8x -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
122 lines
2.3 KiB
C
122 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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* (C) Copyright 2013 - 2018 Xilinx, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <fdtdec.h>
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#include <fpga.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <watchdog.h>
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#include <wdt.h>
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#include <zynqpl.h>
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#include <asm/global_data.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include "../common/board.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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printf("Silicon version:\t%d\n", zynq_get_silicon_version());
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return 0;
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}
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int board_late_init(void)
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{
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int env_targets_len = 0;
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const char *mode;
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char *new_targets;
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char *env_targets;
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if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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debug("Saved variables - Skipping\n");
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return 0;
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}
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if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
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return 0;
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_QSPI:
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mode = "qspi";
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env_set("modeboot", "qspiboot");
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break;
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case ZYNQ_BM_NAND:
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mode = "nand";
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env_set("modeboot", "nandboot");
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break;
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case ZYNQ_BM_NOR:
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mode = "nor";
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env_set("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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mode = "mmc0";
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env_set("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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mode = "jtag pxe dhcp";
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env_set("modeboot", "jtagboot");
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break;
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default:
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mode = "";
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env_set("modeboot", "");
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break;
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}
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/*
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* One terminating char + one byte for space between mode
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* and default boot_targets
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*/
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env_targets = env_get("boot_targets");
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if (env_targets)
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env_targets_len = strlen(env_targets);
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new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
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if (!new_targets)
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return -ENOMEM;
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sprintf(new_targets, "%s %s", mode,
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env_targets ? env_targets : "");
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env_set("boot_targets", new_targets);
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return board_late_init_xilinx();
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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zynq_ddrc_init();
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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zynq_ddrc_init();
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return 0;
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}
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#endif
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