mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
476abb72e0
On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
136 lines
3.2 KiB
C
136 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/nic301.h>
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#include <asm/sections.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/fpga_manager.h>
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#include <mmc.h>
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#include <memalign.h>
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#define FPGA_BUFSIZ 16 * 1024
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo);
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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case 0x3: /* NAND Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
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return BOOT_DEVICE_NAND;
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case 0x4: /* SD/MMC External Transceiver (1.8V) */
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case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
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socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
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return BOOT_DEVICE_MMC1;
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case 0x6: /* QSPI Flash (1.8V) */
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case 0x7: /* QSPI Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
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return BOOT_DEVICE_SPI;
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default:
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printf("Invalid boot device (bsel=%08x)!\n", bsel);
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hang();
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}
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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void spl_board_init(void)
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{
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ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
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/* enable console uart printing */
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preloader_console_init();
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WATCHDOG_RESET();
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arch_early_init_r();
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/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
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if (is_fpgamgr_user_mode()) {
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int ret = config_pins(gd->fdt_blob, "shared");
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if (ret)
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return;
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ret = config_pins(gd->fdt_blob, "fpga");
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if (ret)
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return;
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} else if (!is_fpgamgr_early_user_mode()) {
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/* Program IOSSM(early IO release) or full FPGA */
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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}
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/* If the IOSSM/full FPGA is already loaded, start DDR */
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if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
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ddr_calibration_sequence();
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if (!is_fpgamgr_user_mode())
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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}
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void board_init_f(ulong dummy)
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{
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dcache_disable();
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socfpga_init_security_policies();
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socfpga_sdram_remap_zero();
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socfpga_pl310_clear();
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/* Assert reset to all except L4WD0 and L4TIMER0 */
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socfpga_per_reset_all();
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socfpga_watchdog_disable();
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spl_early_init();
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/* Configure the clock based on handoff */
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cm_basic_init(gd->fdt_blob);
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#ifdef CONFIG_HW_WATCHDOG
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/* release osc1 watchdog timer 0 from reset */
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socfpga_reset_deassert_osc1wd0();
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/* reconfigure and enable the watchdog */
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hw_watchdog_init();
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WATCHDOG_RESET();
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#endif /* CONFIG_HW_WATCHDOG */
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config_dedicated_pins(gd->fdt_blob);
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WATCHDOG_RESET();
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}
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