mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
989ce04999
Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
53 lines
973 B
C
53 lines
973 B
C
/*
|
|
* Copyright 2013 Broadcom Corporation.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/errno.h>
|
|
#include <asm/arch/sysmap.h>
|
|
#include <asm/kona-common/clk.h>
|
|
#include "clk-core.h"
|
|
|
|
/* Enable appropriate clocks for a BSC/I2C port */
|
|
int clk_bsc_enable(void *base)
|
|
{
|
|
int ret;
|
|
char *bscstr, *apbstr;
|
|
|
|
switch ((u32) base) {
|
|
case PMU_BSC_BASE_ADDR:
|
|
/* PMU clock is always enabled */
|
|
return 0;
|
|
case BSC1_BASE_ADDR:
|
|
bscstr = "bsc1_clk";
|
|
apbstr = "bsc1_apb_clk";
|
|
break;
|
|
case BSC2_BASE_ADDR:
|
|
bscstr = "bsc2_clk";
|
|
apbstr = "bsc2_apb_clk";
|
|
break;
|
|
case BSC3_BASE_ADDR:
|
|
bscstr = "bsc3_clk";
|
|
apbstr = "bsc3_apb_clk";
|
|
break;
|
|
default:
|
|
printf("%s: base 0x%p not found\n", __func__, base);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Note that the bus clock must be enabled first */
|
|
|
|
ret = clk_get_and_enable(apbstr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_get_and_enable(bscstr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|