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![Axel Lin](/assets/img/avatar_default.png)
Don't assume slave is always the first member of struct ftssp010_spi. Use to_ftssp010_spi() to ensure free correct address in spi_free_slave(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
499 lines
12 KiB
C
499 lines
12 KiB
C
/*
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* (C) Copyright 2013
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* Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
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* Kuo-Jung Su <dantesu@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/compat.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <spi.h>
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#ifndef CONFIG_FTSSP010_BASE_LIST
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#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
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#endif
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#ifndef CONFIG_FTSSP010_GPIO_BASE
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#define CONFIG_FTSSP010_GPIO_BASE 0
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#endif
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#ifndef CONFIG_FTSSP010_GPIO_LIST
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#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
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#endif
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#ifndef CONFIG_FTSSP010_CLOCK
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#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
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#endif
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#ifndef CONFIG_FTSSP010_TIMEOUT
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#define CONFIG_FTSSP010_TIMEOUT 100
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#endif
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/* FTSSP010 chip registers */
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struct ftssp010_regs {
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uint32_t cr[3];/* control register */
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uint32_t sr; /* status register */
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uint32_t icr; /* interrupt control register */
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uint32_t isr; /* interrupt status register */
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uint32_t dr; /* data register */
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uint32_t rsvd[17];
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uint32_t revr; /* revision register */
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uint32_t fear; /* feature register */
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};
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/* Control Register 0 */
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#define CR0_FFMT_MASK (7 << 12)
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#define CR0_FFMT_SSP (0 << 12)
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#define CR0_FFMT_SPI (1 << 12)
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#define CR0_FFMT_MICROWIRE (2 << 12)
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#define CR0_FFMT_I2S (3 << 12)
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#define CR0_FFMT_AC97 (4 << 12)
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#define CR0_FLASH (1 << 11)
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#define CR0_FSDIST(x) (((x) & 0x03) << 8)
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#define CR0_LOOP (1 << 7) /* loopback mode */
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#define CR0_LSB (1 << 6) /* LSB */
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#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
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#define CR0_FSJUSTIFY (1 << 4)
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#define CR0_OPM_SLAVE (0 << 2)
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#define CR0_OPM_MASTER (3 << 2)
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#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
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#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
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#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
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#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
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#define CR0_SCLKPO (1 << 1) /* clock polarity */
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#define CR0_SCLKPH (1 << 0) /* clock phase */
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/* Control Register 1 */
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#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
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#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
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#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
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/* Control Register 2 */
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#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
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#define CR2_FS (1 << 9) /* CS/FS signal level */
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#define CR2_TXEN (1 << 8) /* tx enable */
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#define CR2_RXEN (1 << 7) /* rx enable */
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#define CR2_RESET (1 << 6) /* chip reset */
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#define CR2_TXFC (1 << 3) /* tx fifo Clear */
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#define CR2_RXFC (1 << 2) /* rx fifo Clear */
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#define CR2_TXDOE (1 << 1) /* tx data output enable */
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#define CR2_EN (1 << 0) /* chip enable */
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/* Status Register */
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#define SR_RFF (1 << 0) /* rx fifo full */
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#define SR_TFNF (1 << 1) /* tx fifo not full */
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#define SR_BUSY (1 << 2) /* chip busy */
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#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
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#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
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/* Feature Register */
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#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
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#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
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#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
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#define FEAR_AC97 (1 << 24)
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#define FEAR_I2S (1 << 25)
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#define FEAR_SPI_MWR (1 << 26)
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#define FEAR_SSP (1 << 27)
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#define FEAR_SPDIF (1 << 28)
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/* FTGPIO010 chip registers */
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struct ftgpio010_regs {
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uint32_t out; /* 0x00: Data Output */
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uint32_t in; /* 0x04: Data Input */
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uint32_t dir; /* 0x08: Direction */
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uint32_t bypass; /* 0x0c: Bypass */
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uint32_t set; /* 0x10: Data Set */
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uint32_t clr; /* 0x14: Data Clear */
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uint32_t pull_up; /* 0x18: Pull-Up Enabled */
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uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
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};
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struct ftssp010_gpio {
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struct ftgpio010_regs *regs;
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uint32_t pin;
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};
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struct ftssp010_spi {
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struct spi_slave slave;
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struct ftssp010_gpio gpio;
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struct ftssp010_regs *regs;
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uint32_t fifo;
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uint32_t mode;
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uint32_t div;
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uint32_t clk;
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uint32_t speed;
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uint32_t revision;
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};
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static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct ftssp010_spi, slave);
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}
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static int get_spi_chip(int bus, struct ftssp010_spi *chip)
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{
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uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
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if (bus >= ARRAY_SIZE(base) || !base[bus])
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return -1;
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chip->regs = (struct ftssp010_regs *)base[bus];
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chip->revision = readl(&chip->regs->revr);
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fear = readl(&chip->regs->fear);
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chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
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return 0;
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}
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static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
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{
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uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
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if (bus >= ARRAY_SIZE(base) || !base[bus])
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return -1;
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chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
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chip->pin = base[bus] & 0x1f;
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/* make it an output pin */
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setbits_le32(&chip->regs->dir, 1 << chip->pin);
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return 0;
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}
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static int ftssp010_wait(struct ftssp010_spi *chip)
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{
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struct ftssp010_regs *regs = chip->regs;
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ulong t;
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/* wait until device idle */
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for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
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if (!(readl(®s->sr) & SR_BUSY))
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return 0;
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}
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puts("ftspi010: busy timeout\n");
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return -1;
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}
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static int ftssp010_wait_tx(struct ftssp010_spi *chip)
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{
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struct ftssp010_regs *regs = chip->regs;
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ulong t;
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/* wait until tx fifo not full */
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for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
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if (readl(®s->sr) & SR_TFNF)
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return 0;
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}
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puts("ftssp010: tx timeout\n");
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return -1;
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}
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static int ftssp010_wait_rx(struct ftssp010_spi *chip)
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{
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struct ftssp010_regs *regs = chip->regs;
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ulong t;
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/* wait until rx fifo not empty */
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for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
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if (SR_RFVE(readl(®s->sr)))
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return 0;
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}
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puts("ftssp010: rx timeout\n");
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return -1;
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}
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static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
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const void *tx_buf, void *rx_buf, int len, uint flags)
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{
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struct ftssp010_regs *regs = chip->regs;
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const uint8_t *txb = tx_buf;
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uint8_t *rxb = rx_buf;
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while (len > 0) {
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int i, depth = min(chip->fifo >> 2, len);
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uint32_t xmsk = 0;
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if (tx_buf) {
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for (i = 0; i < depth; ++i) {
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ftssp010_wait_tx(chip);
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writel(*txb++, ®s->dr);
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}
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xmsk |= CR2_TXEN | CR2_TXDOE;
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if ((readl(®s->cr[2]) & xmsk) != xmsk)
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setbits_le32(®s->cr[2], xmsk);
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}
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if (rx_buf) {
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xmsk |= CR2_RXEN;
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if ((readl(®s->cr[2]) & xmsk) != xmsk)
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setbits_le32(®s->cr[2], xmsk);
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for (i = 0; i < depth; ++i) {
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ftssp010_wait_rx(chip);
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*rxb++ = (uint8_t)readl(®s->dr);
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}
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}
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len -= depth;
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}
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return 0;
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}
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static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
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const void *tx_buf, void *rx_buf, int len, uint flags)
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{
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struct ftssp010_regs *regs = chip->regs;
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const uint8_t *txb = tx_buf;
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uint8_t *rxb = rx_buf;
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while (len > 0) {
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int i, depth = min(chip->fifo >> 2, len);
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uint32_t tmp;
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for (i = 0; i < depth; ++i) {
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ftssp010_wait_tx(chip);
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writel(txb ? (*txb++) : 0, ®s->dr);
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}
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for (i = 0; i < depth; ++i) {
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ftssp010_wait_rx(chip);
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tmp = readl(®s->dr);
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if (rxb)
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*rxb++ = (uint8_t)tmp;
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}
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len -= depth;
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}
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return 0;
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}
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static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
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{
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struct ftssp010_regs *regs = chip->regs;
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struct ftssp010_gpio *gpio = &chip->gpio;
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uint32_t mask;
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/* cs pull high/low */
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if (chip->revision >= 0x11900) {
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mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
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writel(mask, ®s->cr[2]);
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} else if (gpio->regs) {
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mask = 1 << gpio->pin;
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if (high)
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writel(mask, &gpio->regs->set);
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else
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writel(mask, &gpio->regs->clr);
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}
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/* extra delay for signal propagation */
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udelay_masked(1);
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}
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/*
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* Determine if a SPI chipselect is valid.
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* This function is provided by the board if the low-level SPI driver
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* needs it to determine if a given chipselect is actually valid.
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*
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* Returns: 1 if bus:cs identifies a valid chip on this board, 0
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* otherwise.
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*/
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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struct ftssp010_spi chip;
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if (get_spi_chip(bus, &chip))
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return 0;
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if (!cs)
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return 1;
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else if ((cs < 4) && (chip.revision >= 0x11900))
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return 1;
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return 0;
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}
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/*
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* Activate a SPI chipselect.
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* This function is provided by the board code when using a driver
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* that can't control its chipselects automatically (e.g.
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* common/soft_spi.c). When called, it should activate the chip select
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* to the device identified by "slave".
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*/
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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struct ftssp010_regs *regs = chip->regs;
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/* cs pull */
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if (chip->mode & SPI_CS_HIGH)
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ftssp010_cs_set(chip, 1);
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else
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ftssp010_cs_set(chip, 0);
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/* chip enable + fifo clear */
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setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
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}
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/*
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* Deactivate a SPI chipselect.
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* This function is provided by the board code when using a driver
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* that can't control its chipselects automatically (e.g.
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* common/soft_spi.c). When called, it should deactivate the chip
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* select to the device identified by "slave".
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*/
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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/* wait until chip idle */
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ftssp010_wait(chip);
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/* cs pull */
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if (chip->mode & SPI_CS_HIGH)
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ftssp010_cs_set(chip, 0);
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else
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ftssp010_cs_set(chip, 1);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
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{
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struct ftssp010_spi *chip;
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if (mode & SPI_3WIRE) {
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puts("ftssp010: can't do 3-wire\n");
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return NULL;
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}
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if (mode & SPI_SLAVE) {
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puts("ftssp010: can't do slave mode\n");
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return NULL;
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}
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if (mode & SPI_PREAMBLE) {
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puts("ftssp010: can't skip preamble bytes\n");
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return NULL;
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}
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if (!spi_cs_is_valid(bus, cs)) {
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puts("ftssp010: invalid (bus, cs)\n");
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return NULL;
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}
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chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
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if (!chip)
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return NULL;
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if (get_spi_chip(bus, chip))
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goto free_out;
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if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
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puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
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"controlled by tx engine which is not synced with rx engine,\n"
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"so the clock & cs might be shutdown before rx engine\n"
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"finishs its jobs.\n"
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"If possible, please add a dedicated gpio for it.\n");
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}
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chip->mode = mode;
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chip->clk = CONFIG_FTSSP010_CLOCK;
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chip->div = 2;
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if (max_hz) {
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while (chip->div < 0xffff) {
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if ((chip->clk / (2 * chip->div)) <= max_hz)
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break;
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chip->div += 1;
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}
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}
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chip->speed = chip->clk / (2 * chip->div);
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return &chip->slave;
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free_out:
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free(chip);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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free(chip);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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struct ftssp010_regs *regs = chip->regs;
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writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]);
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if (chip->revision >= 0x11900) {
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writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
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®s->cr[0]);
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writel(CR2_TXFC | CR2_RXFC,
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®s->cr[2]);
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} else {
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writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
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®s->cr[0]);
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writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
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®s->cr[2]);
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}
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if (chip->mode & SPI_LOOP)
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setbits_le32(®s->cr[0], CR0_LOOP);
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if (chip->mode & SPI_CPOL)
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setbits_le32(®s->cr[0], CR0_SCLKPO);
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if (chip->mode & SPI_CPHA)
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setbits_le32(®s->cr[0], CR0_SCLKPH);
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spi_cs_deactivate(slave);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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struct ftssp010_regs *regs = chip->regs;
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writel(0, ®s->cr[2]);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct ftssp010_spi *chip = to_ftssp010_spi(slave);
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uint32_t len = bitlen >> 3;
|
|
|
|
if (flags & SPI_XFER_BEGIN)
|
|
spi_cs_activate(slave);
|
|
|
|
if (chip->revision >= 0x11900)
|
|
ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
|
|
else
|
|
ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
|
|
|
|
if (flags & SPI_XFER_END)
|
|
spi_cs_deactivate(slave);
|
|
|
|
return 0;
|
|
}
|