mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-16 09:43:39 +09:00
9f13b6d147
Currently omap_hsmmc driver doesn't use sdcd pin to detect whether the card is present or not. Instead the same pin is used as GPIO to detect card presence. So change the pin mux mode from mmc0_sdcd to gpio0_6. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
374 lines
14 KiB
C
374 lines
14 KiB
C
/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux uart1_pin_mux[] = {
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{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
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{-1},
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};
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static struct module_pin_mux uart2_pin_mux[] = {
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{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
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{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
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{-1},
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};
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static struct module_pin_mux uart3_pin_mux[] = {
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{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
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{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
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{-1},
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};
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static struct module_pin_mux uart4_pin_mux[] = {
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{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
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{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
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{-1},
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};
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static struct module_pin_mux uart5_pin_mux[] = {
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{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
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{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
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{-1},
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};
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static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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{-1},
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};
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux spi0_pin_mux[] = {
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{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
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{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
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{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
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{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
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{-1},
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};
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static struct module_pin_mux gpio0_7_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
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{-1},
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};
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
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{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
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{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
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{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
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{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
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{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
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{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
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{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
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{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
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#endif
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{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
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{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
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{-1},
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};
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#elif defined(CONFIG_NOR)
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static struct module_pin_mux bone_norcape_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
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{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
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{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
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{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
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{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
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{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
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{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
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{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
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{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
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{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
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{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
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{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
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{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
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{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
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{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
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{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
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{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
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{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
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{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
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{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
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{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
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{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
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{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
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{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
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{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
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{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
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{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
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{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
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{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
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{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
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{-1},
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};
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#endif
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#if defined(CONFIG_NOR_BOOT)
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void enable_norboot_pin_mux(void)
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{
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configure_module_pin_mux(bone_norcape_pin_mux);
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}
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#endif
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_uart1_pin_mux(void)
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{
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configure_module_pin_mux(uart1_pin_mux);
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}
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void enable_uart2_pin_mux(void)
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{
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configure_module_pin_mux(uart2_pin_mux);
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}
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void enable_uart3_pin_mux(void)
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{
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configure_module_pin_mux(uart3_pin_mux);
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}
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void enable_uart4_pin_mux(void)
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{
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configure_module_pin_mux(uart4_pin_mux);
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}
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void enable_uart5_pin_mux(void)
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{
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configure_module_pin_mux(uart5_pin_mux);
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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/*
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* The AM335x GP EVM, if daughter card(s) are connected, can have 8
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* different profiles. These profiles determine what peripherals are
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* valid and need pinmux to be configured.
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*/
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#define PROFILE_NONE 0x0
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#define PROFILE_0 (1 << 0)
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#define PROFILE_1 (1 << 1)
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#define PROFILE_2 (1 << 2)
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#define PROFILE_3 (1 << 3)
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#define PROFILE_4 (1 << 4)
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#define PROFILE_5 (1 << 5)
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#define PROFILE_6 (1 << 6)
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#define PROFILE_7 (1 << 7)
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#define PROFILE_MASK 0x7
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#define PROFILE_ALL 0xFF
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/* CPLD registers */
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#define I2C_CPLD_ADDR 0x35
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#define CFG_REG 0x10
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static unsigned short detect_daughter_board_profile(void)
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{
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unsigned short val;
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if (i2c_probe(I2C_CPLD_ADDR))
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return PROFILE_NONE;
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if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
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return PROFILE_NONE;
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return (1 << (val & PROFILE_MASK));
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}
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void enable_board_pin_mux(struct am335x_baseboard_id *header)
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{
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/* Do board-specific muxes. */
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if (board_is_bone(header)) {
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/* Beaglebone pinmux */
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(mii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#elif defined(CONFIG_NOR)
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configure_module_pin_mux(bone_norcape_pin_mux);
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#else
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configure_module_pin_mux(mmc1_pin_mux);
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#endif
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} else if (board_is_gp_evm(header)) {
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/* General Purpose EVM */
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unsigned short profile = detect_daughter_board_profile();
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configure_module_pin_mux(rgmii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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/* In profile #2 i2c1 and spi0 conflict. */
|
|
if (profile & ~PROFILE_2)
|
|
configure_module_pin_mux(i2c1_pin_mux);
|
|
/* Profiles 2 & 3 don't have NAND */
|
|
#ifdef CONFIG_NAND
|
|
if (profile & ~(PROFILE_2 | PROFILE_3))
|
|
configure_module_pin_mux(nand_pin_mux);
|
|
#endif
|
|
else if (profile == PROFILE_2) {
|
|
configure_module_pin_mux(mmc1_pin_mux);
|
|
configure_module_pin_mux(spi0_pin_mux);
|
|
}
|
|
} else if (board_is_idk(header)) {
|
|
/* Industrial Motor Control (IDK) */
|
|
configure_module_pin_mux(mii1_pin_mux);
|
|
configure_module_pin_mux(mmc0_no_cd_pin_mux);
|
|
} else if (board_is_evm_sk(header)) {
|
|
/* Starter Kit EVM */
|
|
configure_module_pin_mux(i2c1_pin_mux);
|
|
configure_module_pin_mux(gpio0_7_pin_mux);
|
|
configure_module_pin_mux(rgmii1_pin_mux);
|
|
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
|
|
} else if (board_is_bone_lt(header)) {
|
|
/* Beaglebone LT pinmux */
|
|
configure_module_pin_mux(i2c1_pin_mux);
|
|
configure_module_pin_mux(mii1_pin_mux);
|
|
configure_module_pin_mux(mmc0_pin_mux);
|
|
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
|
|
configure_module_pin_mux(nand_pin_mux);
|
|
#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
|
|
configure_module_pin_mux(bone_norcape_pin_mux);
|
|
#else
|
|
configure_module_pin_mux(mmc1_pin_mux);
|
|
#endif
|
|
} else {
|
|
puts("Unknown board, cannot configure pinmux.");
|
|
hang();
|
|
}
|
|
}
|